1
Grigorios Magklis, José González, Antonio González: Frequency and voltage scaling architecture. Intel Corporation, Trop Pruner & Hu P C, October 7, 2008: US07434073 (113 worldwide citation)

A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain ...


2
Xavier Vera, Osman Unsal, Oguz Ergin, Jaume Abella, Antonio González: Enhancing reliability of a many-core processor. Intel Corporation, Trop Pruner & Hu P C, December 6, 2011: US08074110 (21 worldwide citation)

In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The alloca ...


3
Fernando Latorre, Jose Gonzalez, Antonio González: Multithreaded clustered microarchitecture with dynamic back-end assignment. Intel Corporation, Kenyon & Kenyon, January 13, 2009: US07478198 (21 worldwide citation)

A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and ...


4
Xavier Vera, Jaume Abella, Osman Unsal, Oguz Ergin, Antonio González: Dynamically estimating lifetime of a semiconductor device. Intel Corporation, Trop Pruner & Hu P C, April 3, 2012: US08151094 (12 worldwide citation)

The present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynam ...


5
Carlos Madriles Gimeno, Carlos García Quinones, Pedro Marcuello, Jesús Sánchez, Fernando Latorre, Antonio González: Enabling speculative state information in a cache coherency protocol. Intel Corporation, Trop Pruner & Hu P C, May 22, 2012: US08185700 (10 worldwide citation)

In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thre ...


6
Qiong Cai, José González, Pedro Chaparro Monferrer, Grigorios Magklis, Antonio González: Thread migration to improve power efficiency in a parallel processing environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 19, 2011: US07930574 (9 worldwide citation)

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing co ...


7
Pedro Lopez, F Jesús Sánchez, Josep M Codina, Enric Gibert, Fernando Latorre, Grigorios Magklis, Pedro Marcuello, Antonio González: Replacement policy for hot code detection. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 17, 2013: US08612698 (9 worldwide citation)

Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution freq ...


8
Enric Gibert, Josep M Codina, Fernando Latorre, José Alejandro Piñeiro, Pedro López, Antonio González: Access of register files of other threads using synchronization. Intel Corporation, Trop Pruner & Hu P C, September 4, 2012: US08261046 (6 worldwide citation)

In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a seco ...


9
Hong Wang, Tor M Aamodt, Pedro Marcuello, Jared W Stark IV, John P Shen, Antonio González, Per Hammarlund, Gerolf F Hoflehner, Perry H Wang, Steve Shih wei Liao: Speculative multi-threading for instruction prefetch and/or trace pre-build. Intel Corporation, David P McAbee, October 12, 2010: US07814469 (6 worldwide citation)

The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.


10
Fernando Latorre, José González, Antonio González: Register allocation technique. Intel Corporation, Trop Pruner & Hu P C, December 25, 2007: US07313675 (5 worldwide citation)

A technique for allocating register resources within a microprocessor. More particularly, embodiments of the invention pertain to a register allocation technique within a microprocessor for multiple-threads of instructions or groups of micro-operations (“uops”).