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Terry L Biggs, Antonio A Lagana: Data processor having a cache memory capable of being used as a linear ram bank. Motorola, Charlotte B Whitaker, April 25, 1995: US05410669 (67 worldwide citation)

A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage o ...


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Terry L Biggs, Antonio A Lagana: A data processor having a cache memory capable of being used as a linear ram bank. Motorola, January 21, 1995: TW239200

A data processing system (10) having a dual purpose memory (14) ?comprising multiple cache sets. Each cache set can be ?individually configured as either a cache set or as a static ?random access memory (SRAM) bank. Based upon the configuration of ?the set, the tag store array (58) is used for stora ...


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