1
Catherine L Barnaby, Richard J Gammack, Anthony I Stansfield: Cam with additional row cells connected to match line. SGS Thomson Microelectronics, Felsman Bradley Gunter & Dillon, February 13, 1996: US05491703 (142 worldwide citation)

A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when ...


2
Anthony I Stansfield: Programmable logic device with memory that can store routing data of logic data. SGS Thomson Microelectronics, Felsman Bradley Gunter & Dillon, December 5, 1995: US05473267 (141 worldwide citation)

A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator. This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array.


3
Anthony I Stansfield: Memory device that functions as a content addressable memory or a random access memory. Inmos, Chancellor Masters and Scholars of the University of Oxford, Felsman Bradley Gunter & Dillon, April 18, 1995: US05408434 (43 worldwide citation)

A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator. This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array.


4
Anthony I Stansfield, Catherine L Barnaby, Richard J Gammack, Roger M Shepherd: Cache memory system including a RAM for storing data and CAM cell arrays for storing virtual and physical addresses. Inmos, Felsman Bradley Gunter & Dillon, November 12, 1996: US05574875 (23 worldwide citation)

A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses w ...


5
Alan Marshall, Andrea Olgiati, Anthony I Stansfield: Methods and systems for reducing leakage current in semiconductor circuits. Elixent, Orrick Herrington & Sutcliffe, September 20, 2005: US06946903 (9 worldwide citation)

Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure th ...


6
Anthony I Stansfield: Loosely-biased heterogeneous reconfigurable arrays. Panasonic Corporation, Orrick Herrington & Sutcliffe, December 30, 2008: US07471643 (8 worldwide citation)

A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other cl ...


7
Nicholas John Charles Ray, Andrea Olgiati, Anthony I Stansfield, Alan D Marshall: Loosely-biased heterogeneous reconfigurable arrays. Panasonic Corporation, Orrick Herrington & Sutcliffe, December 2, 2008: US07461234 (5 worldwide citation)

A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other cl ...


8
Alan Marshall, Andrea Olgiati, Anthony I Stansfield: Methods and systems for reducing leakage current in semiconductor circuits. Panasonic Europe, Orrick Herrington & Sutcliffe, January 1, 2008: US07315201 (5 worldwide citation)

Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure th ...


9
Anthony I Stansfield, Alan D Marshall: Low-power voltage modulation circuit for pass devices. Elixent, Orrick Herrington & Sutcliffe, February 22, 2005: US06859084 (5 worldwide citation)

Power supply voltages are selectively modulated to correspond with degraded input voltages to a logic device. Modulated power supply voltages are provided to transistors within the logic device, so that the degraded input voltages supplied to the transistors are sufficient to turn the transistors su ...


10
Alan Marshall, Andrea Olgiati, Anthony I Stansfield: Methods and systems for reducing leakage current in semiconductor circuits. Panasonic Europe, Orrick Herrington & Sutcliffe, June 19, 2007: US07233197 (4 worldwide citation)

Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure th ...