81
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, September 22, 2015: US09141555

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


82
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Nicholson De Vos Webster & Elliot, January 15, 2019: US10180911

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


83
Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M Bennett, Andrew V Anderson, Erik C Cota Robles: Delivering interrupts directly to a virtual processor. Intel Corporation, Trop Pruner & Hu P C, September 13, 2016: US09442868

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the i ...


84
Sanjay K Kumar, Rajesh M Sankaran, Subramanya R Dulloor, Andrew V Anderson: Instruction and logic for flush-on-fail operation. Intel Corporation, Alliance IP, January 30, 2018: US09880932

A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory man ...


85
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Richard A Uhlig, Lawrence O Smith, Barry E Huntley: Virtualization event processing in a layered virtualization architecuture. Intel Corporation, Nicholson De Vos Webster & Elliott, August 2, 2016: US09405565

Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determin ...


86
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Richard A Uhlig, Lawrence O Smith, Barry E Huntley: Virtualization event processing in a layered virtualization architecture. Nicholson De Vos Webster & Elliott, January 12, 2016: US09235434

Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determin ...


87
Rajesh M Sankaran, Altug Koker, Philip R Lantz, Asit K Mallick, James B Crossland, Aditya Navale, Gilbert Neiger, Andrew V Anderson: Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory. Intel Corporation, Nicholson De Vos Webster & Elliott, March 13, 2018: US09916257

Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a m ...


88
Sanjay Kumar, Rajesh M Sankaran, Subramanya R Dulloor, Dheeraj R Subbareddy, Andrew V Anderson: Computing method and apparatus with persistent memory. Intel Corporation, Schwabe Williamson & Wyatt P C, July 25, 2017: US09715453

Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processor ...


89
Gilbert Neiger, Andrew V Anderson, Richard A Uhlig, David M Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli: Monitoring the operation of a processor. Intel Corporation, Nicholson De Vos Webster & Elliott, January 2, 2018: US09858167

Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root ...


90
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Richard A Uhlig, Lawrence O Smith, Barry E Huntley: Virtualization event processing in a layered virtualization architecture. Intel Corporation, Thomas R Lane, October 10, 2017: US09785485

Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determin ...