51
Erik C Cota Robles, Steven M Bennett, Andrew V Anderson, Sebastian Schoenberg: Controlling virtual machines based on performance counters. Intel Corporation, Trop Pruner & Hu P C, August 26, 2014: US08819699 (3 worldwide citation)

Embodiments of apparatuses, methods, and systems for controlling virtual machines based on performance counters are disclosed. In one embodiment, an apparatus includes an event counter, a comparator, and virtualization control logic. The event counter is to keep an event count based on the number of ...


52
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Richard A Uhlig, Lawrence O Smith, Barry E Huntley: Virtual interrupt processing in a layered virtualization architecture. Thomas R Lane, July 5, 2011: US07975267 (3 worldwide citation)

Embodiments of apparatuses, methods, and systems for processing virtual interrupts in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to transfer con ...


53
Andrew V Anderson: DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces. Intel Corporation, Kenyon & Kenyon, November 18, 2003: US06651115 (3 worldwide citation)

In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communicati ...


54
Steven M Bennett, Andrew V Anderson, Erik Cota Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig: Method and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 17, 2009: US07620949 (2 worldwide citation)

In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check ...


55
Erik C Cota Robles, Gilbert Neiger, Steven M Bennett, Andrew V Anderson: Virtualizing performance counters. Intel Corporation, Trop Pruner & Hu P C, December 10, 2013: US08607228 (2 worldwide citation)

Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is store a counter ...


56
Steven M Bennett, Andrew V Anderson, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Xiang Zou, Lawrence Smith, Scott Rodgers: Optimizing processor-managed resources based on the behavior of a virtual machine monitor. Intel Corporation, Thomas R Lane, October 15, 2013: US08561068 (2 worldwide citation)

In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.


57
Ravi L Sahita, David M Durham, Gilbert Neiger, Andrew V Anderson, Scott D Rodgers: Low latency virtual machine page table management. Intel Corporation, Thomas R Lane, August 2, 2016: US09405570 (2 worldwide citation)

Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claime ...


58
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron B Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, December 3, 2013: US08601233 (1 worldwide citation)

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


59
Ravi L Sahita, Gilbert Neiger, David M Durham, Vedvyas Shanbhogue, Michael Lemay, Ido Ouziel, Stanislav Shwartsman, Barry Huntley, Andrew V Anderson: Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure. Intel Corporation, Lowenstein Sandler, October 17, 2017: US09792222 (1 worldwide citation)

Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associ ...


60
Sanjay Kumar, Rajesh M Sankaran, Subramanya R Dulloor, Andrew V Anderson: Instruction and logic for flush-on-fail operation. Intel Corporation, Baker Botts L, February 7, 2017: US09563557 (1 worldwide citation)

A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory man ...