1
Glenn J Hinton, David B Papworth, Andrew F Glew, Michael A Fetterman, Robert P Colwell: Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 24, 1998: US05721855 (179 worldwide citation)

A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an in ...


2
Derrick Lin, Romamohan R Vakkalagadda, Andrew F Glew, Larry M Mennemeier, Alexander D Peleg, David Bistry, Millind Mittal, Carole Dulong, Eiichi Kowashi, Benny Eitan: Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 22, 1998: US05852726 (102 worldwide citation)

A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to ...


3
Andrew F Glew, Haitham Akkary: Method and apparatus for handling speculative memory access operations. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 21, 1999: US05956753 (82 worldwide citation)

The method and apparatus are employed within a microprocessor capable of generating speculative memory accesses instructions. Certain instructions access memory locations containing speculatable information while others access memory locations containing non-speculatable information. Memory-type val ...


4
David B Papworth, Michael A Fetterman, Andrew F Glew, Lawrence O Smith III, Michael M Hancock, Beth Schultz: Apparatus and method for handling string operations in a pipelined processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 1995: US05404473 (78 worldwide citation)

In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a ...


5
Doron Orenstein, Ofri Wechsler, Millind Mittal, Andrew F Glew, Larry M Mennemeier, Alexander D Peleg, David Bistry, Carole Dulong, Eiichi Kowashi, Benny Eitan, Derrick Lin, Ramamohan R Vakkalagadda: Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 10, 1998: US05835748 (72 worldwide citation)

A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is pro ...


6
Andrew F Glew, Glenn J Hinton: Method and apparatus for processing memory-type information within a microprocessor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 12, 1998: US05751996 (72 worldwide citation)

A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-ins ...


7
Jeffrey M Abramson, David B Papworth, Haitham H Akkary, Andrew F Glew, Glenn J Hinton, Kris G Konigsfeld, Paul D Madland: Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations. May 12, 1998: US05751983 (64 worldwide citation)

A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequentl ...


8
Haitham Akkary, Mandar S Joshi, Rob Murray, Brent E Lince, Paul D Madland, Andrew F Glew, Glenn J Hinton: Method and apparatus for implementing a single clock cycle line replacement in a data cache unit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 11, 1996: US05526510 (64 worldwide citation)

The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back t ...


9
Andrew F Glew, Larry M Mennemeier, Alexander D Peleg, David Bistry, Millind Mittal, Carole Dulong, Eiichi Kowashi, Benny Eitan, Derrick Lin, Ramamohan R Vakkalagadda: Executing different instructions that cause different data type operations to be performed on single logical register file. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 23, 1997: US05701508 (63 worldwide citation)

A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to ...


10
Jeffery M Abramson, Haitham Akkary, Andrew F Glew, Glenn J Hinton, Kris G Konigsfeld, Paul D Madland: Method and apparatus for blocking execution of and storing load operations during their execution. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 9, 1999: US05881262 (61 worldwide citation)

A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and ...