1
Mark A Ross, Sun Den Chen, Andreas V Bechtolsheim: Logical operation unit for packet processing. Cisco Technology, The Law Office of Kirk D Williams, December 2, 2003: US06658002 (198 worldwide citation)

An apparatus and method for performing logical operations on information in the communications protocol stack, such as the transport layer (L4) port numbers, characterizing a received packet or frame of data in a data communications device such as a router or switch. The results of the logical opera ...


2
Andreas V Bechtolsheim, Howard M Frazier, Thomas J Edsall: Multi-function high-speed network interface. Cisco Technology, File EE Patents com, Jay A Chesavage, August 11, 2009: US07573916 (170 worldwide citation)

A high speed communications interface divides data into a plurality of lanes, each lane encoded with clocking information, serialized, and sent to an interface. During cycles when there is no available data to send, IDLE_EVEN and IDLE_ODD cells are sent on alternating cycles. Data is transmitted by ...


3
David R Cheriton, Andreas V Bechtolsheim: Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network. Cisco Systems, Oblon Spivak McClelland Maier & Neustadt P C, July 18, 2000: US06091725 (150 worldwide citation)

The invention provides an enhanced datagram packet switched computer network. The invention processes network datagram packets in network devices as separate flows, based on the source-destination address pair in the datagram packet. As a result, the network can control and manage each flow of datag ...


4
Andreas V Bechtolsheim, David R Cheriton: Access control list processing in hardware. Cisco Technology, Skjerven Morrill MacPherson, April 23, 2002: US06377577 (102 worldwide citation)

The invention provides for hardware processing of ACLs and thus hardware enforcement of access control. A sequence of access control specifiers from an ACL are recorded in a CAM, and information from the packet header is used to attempt to match selected source and destination IP addresses or subnet ...


5
Andreas V Bechtolsheim, David R Cheriton: Per-flow dynamic buffer management. Cisco Technology, Campbell Stephenson Ascolese, February 4, 2003: US06515963 (86 worldwide citation)

The present invention provides a per-flow dynamic buffer management scheme for a data communications device. With per-flow dynamic buffer limiting, the header information for each packet is mapped into an entry in a flow table, with a separate flow table provided for each output queue. Each flow tab ...


6
Andreas V Bechtolsheim, David R Cheriton: Single-chip architecture for shared-memory router. Cisco Technology, Skjerven Morrill MacPherson, January 29, 2002: US06343072 (84 worldwide citation)

The invention provides a single-chip method. The method includes a memory shared among packet buffers for receiving packets, packet buffers for transmitting packets, and packet header buffers for packet forwarding lookup. Accesses to that shared memory are multiplexed and prioritized. Packet recepti ...


7
Mark Ross, Andreas V Bechtolsheim: Block mask ternary cam. Cisco Technology, May 14, 2002: US06389506 (61 worldwide citation)

A method and system for flexible matching of data in a CAM that does not use the overhead of one mask bit for each matched value bit. The entries of the CAM are logically grouped in a set of blocks, each block having a single mask that applies to all entries in the block. Each block includes a prede ...


8
Mark A Ross, Andreas V Bechtolsheim: Block mask ternary CAM. Cisco Technology, The Law Office of Kirk D Williams, May 18, 2004: US06738862 (58 worldwide citation)

The invention provides a method and system for flexible matching of data in a CAM, that does not use the overhead of one mask bit for each matched value bit. The entries of the CAM are logically grouped in a set of blocks, each block having a single mask that applies to all entries in the block. Eac ...


9
Stewart Findlater, Andreas V Bechtolsheim: Serial media independent interface. Cisco Technology, Beyer Weaver & Thomas, May 7, 2002: US06385208 (58 worldwide citation)

Provided is a 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time ...


10
Andreas V Bechtolsheim, David R Cheriton: Packet processing engine architecture. Cisco Technology, Hickman Palermo Truong & Becker, May 15, 2007: US07218632 (40 worldwide citation)

The invention provides a method and system for packet processing, in which a router (or switch) is capable of quickly processing incoming packets, thus performing level 2, 3, and 4 routing and additional services, in real time. A system includes a packet processing engine (PPE), having elements for ...