1
Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk: Scalable architecture based on single-chip multiprocessing. Hewlett Packard Development Company, December 23, 2003: US06668308 (129 worldwide citation)

A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. ...


2
Kourosh Gharachorloo, Luiz A Barroso, Mosur K Ravishankar, Robert J Stets Jr, Andreas Nowatzyk: Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system. Hewlett Packard Development Company, September 16, 2003: US06622217 (81 worldwide citation)

The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory ...


3
Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk: Method and system for exclusive two-level caching in a chip-multiprocessor. Hewlett Packard Development Company, April 20, 2004: US06725334 (75 worldwide citation)

To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order ...


4
Kourosh Gharachorloo, Luiz A Barroso, Robert J Stets Jr, Mosur K Ravishankar, Andreas Nowatzyk: System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system. Hewlett Packard Development Company, February 24, 2004: US06697919 (60 worldwide citation)

A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of informati ...


5
Luiz A Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K Ravishankar, Robert J Stets Jr: Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants. Hewlett Packard Development Company, January 6, 2004: US06675265 (57 worldwide citation)

A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an assoc ...


6
Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk: Scalable architecture based on single-chip multiprocessing. Hewlett Packard Development Company, January 17, 2006: US06988170 (50 worldwide citation)

A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. ...


7
Luiz A Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert J Stets, Mosur K Ravishankar: System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing. Hewlett Packard Development Company, October 21, 2003: US06636949 (48 worldwide citation)

In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsi ...


8
Luiz A Barroso, Kourosh Gharachorloo, Andreas Nowatzyk: System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system. Hewlett Packard Development Company, April 20, 2004: US06725343 (37 worldwide citation)

Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. T ...


9
Ashley Saulsbury, Andreas Nowatzyk, Fong Pong: Integrated processor/memory device with victim data cache. Sun Microsystems, Stephen M Flehr Hohbach Test Albritton & Herbert Knauer, May 4, 1999: US05900011 (28 worldwide citation)

An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. ...


10
Andreas Nowatzyk, Rod Fleck: Passive matrix quantum dot display. Microsoft Corporation, Micah Goldsmith, Sergey Lamansky, Micky Minhas, April 8, 2014: US08693087 (22 worldwide citation)

A system and method for operating a light emitting device utilizing charged quantum dots is described. In one embodiment, charged quantum dots are suspended in a liquid between an excitation plate and a cover plate. The excitation plate carries short-wave excitation light. Charged quantum dots near ...