1
Neal Mielke, Gregory E Atwood, Amit Merchant: Method of repairing overerased cells in a flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 17, 1993: US05237535 (133 worldwide citation)

A method of repairing overerased cells in a flash memory array including a column having a first cell and a second cell is described. Repair begins by determining whether a first cell is overerased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is o ...


2
Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu: Method and apparatus for entering and exiting multiple threads within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 3, 2005: US06889319 (79 worldwide citation)

A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a func ...


3
Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur: Method and apparatus for processing an event occurrence within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 17, 2002: US06496925 (75 worldwide citation)

A method includes detecting a first event occurrence for a first thread being processed within a multithreaded processor. Responsive to the detection of this first event occurrence, a second thread being processed within the multithreaded processor is monitored to detect a clearing point for this se ...


4
Amit Merchant, Mickey L Fandrich, Neal Mielke: Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy. Intel Corporation, Blakely Sokoloff Taylor Zafman, December 27, 1994: US05377147 (67 worldwide citation)

Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower threshold voltage levels than good cells but ensuring the threshold voltage levels of shorted cells are high ...


5
Amit Merchant, Mickey L Fandrich, Neal Mielke: Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 5, 1994: US05327383 (67 worldwide citation)

Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control ...


6
Amit Merchant, Mickey L Fandrich, Neal Mielke: Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 13, 1994: US05347489 (56 worldwide citation)

A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a no ...


7
Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur: Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 2, 2006: US07039794 (38 worldwide citation)

A method includes detecting a first pending event related a first thread being processed within a multithreaded processor. Responsive to the detection of the first pending event, a second thread being processed within the multithreaded processor is monitored to detect an event handling point for the ...


8
Amit Merchant, Selim Bilgin, Brinkley Sprunt: Method and apparatus to monitor the performance of a processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 3, 2004: US06772322 (36 worldwide citation)

A method and apparatus to monitor the performance of a processor. A performance specifier specifies a performance data corresponding to the performance. The performance data includes an event and an instruction causing the event. A tag generator is coupled to the performance specifier to generate a ...


9
Nitin V Sarangdhar, Wen Han Wang, Michael W Rhodehamel, James M Brayton, Amit Merchant, Matthew A Fisch: Computer system that maintains system wide cache coherency during deferred communication transactions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 28, 1997: US05682516 (26 worldwide citation)

A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete t ...


10
Peter MacWilliams, Nitin V Sarangdhar, Matthew Fisch, Amit Merchant: Method and apparatus for snoop stretching using signals that convey snoop results. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 5, 1996: US05572703 (23 worldwide citation)

A protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus transaction requests and at least one snooping agent for monitoring transaction requests and issuing bus signals onto an external bus. The bus transactions are timed by a b ...