1
Amit A Merchant, Darrell D Boggs, David J Sager: Multi-threading for a processor utilizing a replay queue. Intel Corporation, Antonelli Terry Stout & Kraus, May 7, 2002: US06385715 (78 worldwide citation)

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly ...


2
Amit A Merchant: Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 6, 1999: US05893151 (59 worldwide citation)

An apparatus for maintaining cache coherency for snoop operations includes a processor core for fetching, decoding, and executing instructions, a data cache coupled to the processor core for providing data to the processor core and for receiving data from the processor core, and a system bus couplin ...


3
Amit A Merchant, David J Sager, Darrell D Boggs: Computer processor with a replay system. Intel Corporation, Kenyon & Kenyon, December 19, 2000: US06163838 (43 worldwide citation)

A computer processor includes a multiplexer having a first input, a second input, and an output, and a scheduler coupled to the multiplexer first input. The processor further includes an execution unit coupled to the multiplexer output. The execution unit is adapted to receive a plurality of instruc ...


4
Amit A Merchant, Darrell D Buggs, David J Sager: Storing of instructions relating to a stalled thread. Intel Corporation, Kenyon & Kenyon, September 14, 2004: US06792446 (33 worldwide citation)

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly ...


5
Amit A Merchant: Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 23, 1999: US05875467 (30 worldwide citation)

A method of maintaining cache coherency for snoop operations includes initiating a first snoop operation in response to a snoop request while one or more previous snoop operations are pending in a queue. Furthermore, one or more subsequent snoop operations can be queued, wherein a step of determinin ...


6
Amit A Merchant, David J Sager: Scheduling operations using a dependency matrix. Intel Corporation, Kenyon & Kenyon, December 25, 2001: US06334182 (29 worldwide citation)

A method and apparatus for scheduling operations using a dependency matrix. A child operation, such as a micro-operation, is received for scheduling. The child operation is dependent on the completion of a parent operation, such as when one of the child operation's sources is the parent operati ...


7
Amit A Merchant, Darrell D Boggs, David J Sager: Processor with a replay system that includes a replay queue for improved throughput. Intel Corporation, Kenyon & Kenyon, April 3, 2007: US07200737 (29 worldwide citation)

A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly ...


8
Amit A Merchant, David J Sager, Darrell D Boggs, Michael D Upton: Computer processor with a replay system having a plurality of checkers. Intel, Kenyon & Kenyon, July 25, 2000: US06094717 (22 worldwide citation)

A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the ...


9
Amit A Merchant: Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 30, 1999: US05890200 (21 worldwide citation)

An apparatus for maintaining cache coherency for snoop operations includes a snoop scheduler coupled to receive addresses from a system bus. The snoop scheduler utilizes a content addressable memory array. The snoop scheduler determines if snoop operations are orthogonal and schedules one or more ou ...


10
Amit A Merchant, David J Sager, James D Allen: Processor including replay queue to break livelocks. Intel Corporation, John F Kacvinsky, August 31, 2004: US06785803 (21 worldwide citation)

A technique is provided for breaking a stalled condition or livelock in a processor having a replay queue. A livelock or stalled condition is detected. One or more instructions are temporarily stored in a replay queue. A release or break in the livelock or stalled condition is detected, and the inst ...