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Shebanow Michael C, Alsup Mitchell: A data processor for performing simultaneous instruction retirement and backtracking.. Motorola, November 25, 1992: EP0515166-A1 (42 worldwide citation)

A data processing system (10) which has more general purpose physical registers than architectural (logical) registers. The system (10) uses a register inventory system (90) to monitor the allocation state changes of physical registers in a register file (37). As a sequencer (20) issues instructions ...


2
Shebanow Michael C, Alsup Mitchell K: A data processor having a logical register content-addressable memory.. Motorola, November 25, 1992: EP0514763-A2 (15 worldwide citation)

A data processing system (10) has more general purpose physical registers than architectural (logical) registers. The system (10) uses a logical register content-addressable memory (LRCAM) (40) to map logical registers to physical registers, and to monitor the assignment of physical registers. Each ...


3
Alsup Mitchell, Becker Michael C: Data processing system and method for performing register renaming having back-up capability.. Motorola, July 20, 1994: EP0606697-A1 (7 worldwide citation)

In a data processing system, a method for performing register renaming with back-up capability. A register renaming apparatus (18) comprises a logical-physical (LP) register map (30), a free list (32), and an internal swap bus (90) for exchanging information between the two. The register renaming ha ...


4
Sander Benjamin T, Ramani Krishnan V, Haddad Ramsey W, Alsup Mitchell: System and method for validating a memory file that links speculative results of load operations to register values. Advanced Micro Devices, Sander Benjamin T, Ramani Krishnan V, Haddad Ramsey W, Alsup Mitchell, sDRAKE Paul S, November 24, 2005: WO/2005/111794 (5 worldwide citation)

A system and method for linking speculative results of load operations to register values. A system (100) includes a memory file (132) including an entry (220) configured to store a first addressing pattern (206) and a first tag (208). The memory file (132) is configured to compare the first address ...


5
Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T: System and method for handling exceptional instructions in a trace cache based processor. Advanced Micro Devices, Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T, DRAKE Paul S, May 6, 2005: WO/2005/041024 (4 worldwide citation)

A system may include an instruction cache (106), a trace cache (160) including a plurality of trace cache entries (162), and a trace generator (170) coupled to the instruction cache (106) and the trace cache (160). The trace generator (170) may be configured to receive a group of instructions output ...


6
Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T: System and method for handling exceptional instructions in a trace cache based processor. Advanced Micro Devices, July 26, 2006: GB2422464-A (3 worldwide citation)

A system may include an instruction cache (106), a trace cache (160) including a plurality of trace cache entries (162), and a trace generator (170) coupled to the instruction cache (106) and the trace cache (160). The trace generator (170) may be configured to receive a group of instructions output ...


7
Alsup Mitchell, Smaus Gregory William: Transitioning from instruction cache to trace cache on label boundaries. Advanced Micro Devices, September 6, 2006: GB2423852-A (2 worldwide citation)

Various embodiments of methods and systems for implementing a microprocessor (100) that includes a trace cache (160) and attempts to transition fetching from instruction cache (106) to trace cache (160) only on label boundaries are disclosed. In on embodiment, a microprocessor (100) may include an i ...


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Alsup Mitchell K: Method for proactive synchronization within a computer system. Advanced Micro Devices, July 2, 2008: GB2445294-A

A method for providing proactive synchronization in a computer system (100) includes a processor (18A, 18B) requesting exclusive access to a given memory resource (314A-314D). The request may include one or more addresses associated with the given memory resource. The method also includes comparing ...


10
Sander Benjamin T, Ramani Krishnan V, Haddad Ramsey W, Alsup Mitchell: System and method for validating a memory file that links speculative results of load operations to register values. Advanced Micro Devices, February 28, 2007: GB2429557-A

A system and method for linking speculative results of load operations to register values. A system (100) includes a memory file (132) including an entry (220) configured to store a first addressing pattern (206) and a first tag (208). The memory file (132) is configured to compare the first address ...