1
Veeraraghavan S Basker, Kangguo Cheng, Bruce B Doris, Johnathan E Faltermeier, Ali Khakifirooz: High-K/metal gate CMOS finFET with improved pFET threshold voltage. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello Esq, August 9, 2011: US07993999 (46 worldwide citation)

A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the expose ...


2
Stephen W Bedell, Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Devendra K Sadana, Ghavam G Shahidi: Strained CMOS device, circuit and method of fabrication. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello Esq, May 1, 2012: US08169025 (27 worldwide citation)

A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p- ...


3
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Ghavam G Shahidi: High-performance FETs with embedded stressors. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, September 20, 2011: US08022488 (17 worldwide citation)

A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor materi ...


4
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G Shahidi: Stressed Fin-FET devices with low contact resistance. International Business Machines Corporation, George Sai Halasz, Louis J Percello, June 26, 2012: US08207038 (16 worldwide citation)

A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is for ...


5
Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam Shahidi: Raised source/drain structure for enhanced strain coupling from stress liner. International Business Machines Corporation, Jose Gutman, Thomas Grzesik, Fleit Gibbons Gutman Bongini & Bianco PL, December 25, 2012: US08338260 (14 worldwide citation)

A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adja ...


6
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G Shahidi: Stressed Fin-FET devices with low contact resistance. International Business Machines Corporation, George Sai Halasz, Louis J Percello, March 19, 2013: US08399938 (12 worldwide citation)

An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET dev ...


7
Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Alexander Reznicek: FinFET structures having silicon germanium and silicon fins. International Business Machines Corporation, Daniel P Morris, Otterstedt Ellenbogen & Kammer, March 31, 2015: US08993399 (12 worldwide citation)

A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon lay ...


8
Ruilong Xie, Xiuyu Cai Jr, Kangguo Cheng, Ali Khakifirooz: Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation. GLOBALFOUNDRIES, Williams Morgan & Amerson P C, September 24, 2013: US08541274 (12 worldwide citation)

In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial ...


9
Veeraraghavan S Basker, Bruce Doris, Ali Khakifirooz, Tenko Yamashita, Chun chen Yeh: Forming strained and relaxed silicon and silicon germanium fins on the same wafer. International Business Machines Corporation, Fleit Gibbons Gutman Bongini & Bianco PL, Thomas Grzesik, February 10, 2015: US08951870 (11 worldwide citation)

Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the s ...


10
Stephen W Bedell, Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Pranita Kulkarni, Katherine L Saenger: Strained devices, methods of manufacture and design structures. International Business Machines Corporation, Matthew Zehrer, Roberts Mlotkowski Safran & Cole P C, July 16, 2013: US08486776 (11 worldwide citation)

Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe lay ...



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