1
Alfred J Reich, Kevin D Lucas, Michael E Kling, Warren D Grobman, Bernard J Roman: One dimensional lithographic proximity correction using DRC shape functions. Motorola, Daniel D HIll, May 4, 1999: US05900340 (196 worldwide citation)

Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the el ...


2
Kevin D Lucas, Michael E Kling, Alfred J Reich, Chong Cheng Fu, James Morrow: Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same. Motorola, J Gustav Larson, December 15, 1998: US05849440 (40 worldwide citation)

A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lit ...


3
Alfred J Reich, Warren D Grobman, Bernard J Roman, Kevin D Lucas, Clyde H Browning, Michael E Kling: Two dimensional lithographic proximity correction using DRC shape functions. Motorola, Bruce E Hayden, July 6, 1999: US05920487 (36 worldwide citation)

Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dimension of the elements within the circuit desi ...


4
Kevin Lucas, Michael E Kling, Bernard J Roman, Alfred J Reich: Methods of designing a reticle and forming a semiconductor device therewith. Motorola, George R Meyer, Sandra L Godsey, October 27, 1998: US05827625 (19 worldwide citation)

A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device feat ...


5
Edward O Travis, Aykut Dengi, Sejal Chheda, Tat Kwan Yu, Mark S Roberton, Ruiqi Tian, Robert E Boone, Alfred J Reich: Method for adding features to a design layout and process for designing a mask. Motorola, July 15, 2003: US06593226 (15 worldwide citation)

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature pat ...


6
Warren D Grobman, Ruoping Wang, Alfred J Reich: Method and apparatus for forming a pattern on an integrated circuit using differing exposure characteristics. Motorola, James L Clingan Jr, Kim Marie Vo, August 12, 2003: US06605395 (4 worldwide citation)

A method of patterning a wafer using four areas with differing exposure characteristics is disclosed. Two areas are phase shifted relative to the other two areas in order to create unexposed areas on the integrated circuit. Two different areas have polarizations orthogonal to each other, are frequen ...


7
Edward O Travis, Aykut Dengi, Sejal Chheda, Tat Kwan Yu, Mark S Roberton, Ruiqi Tian, Robert E Boone, Alfred J Reich: Method for adding features to a design layout and process for designing a mask. Motorola, Austin Intellectual Property, May 2, 2002: US20020050655-A1

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature pat ...


8
Warren D Grobman, Ruoping Wang, Alfred J Reich: Method and apparatus for forming a pattern on an integrated circuit using differing exposure characteristics. Motorola, Austin Intellectual Property, December 26, 2002: US20020197541-A1

A method of patterning a wafer using four areas with differing exposure characteristics is disclosed. Two areas are phase shifted relative to the other two areas in order to create unexposed areas on the integrated circuit. Two different areas have polarizations orthogonal to each other, are frequen ...