1
Alfred E Dunlop, Thaddeus J Gabara, Scott C Knauer: Digitally controlled element sizing. AT&T Bell Laboratories, Henry T Brendzel, March 16, 1993: US05194765 (163 worldwide citation)

Effective control of impedance values in integrated circuit applications is achieved with an integrated circuit transistor whose size is digitally controlled. The digitally controlled size is achieved, for example, with a parallel interconnection of MOS transistors. In one application, the digitally ...


2
Alfred E Dunlop, Brian W Kernighan: Placement of components on circuit substrates. AT&T Bell Laboratories, Robert O Nimtz, March 18, 1986: US04577276 (117 worldwide citation)

In laying out integrated circuits on a substrate, the placement of the components relative to each other is important in minimizing conductor area and hence chip area. Large scale integration often uses polycells which are lined up in rows to realize the digital logic circuitry. A partitioning proce ...


3
Alfred E Dunlop, John P Fishburn: Transistor sizing system for integrated circuits. American Telephone and Telegraph Company AT&T Bell Laboratories, Henry T Brendzel, May 2, 1989: US04827428 (103 worldwide citation)

A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit tha ...


4
Alfred E Dunlop, Thaddeus J Gabara, Scott C Knauer: Digitally controlled element sizing. AT&T Bell Laboratories, Henry T Brendzel, Christopher N Malvone, March 29, 1994: US05298800 (52 worldwide citation)

Effective control of impedance values in integrated circuit applications is achieved with an integrated circuit transistor whose size is digitally controlled. The digitally controlled size is achieved, for example, with a parallel interconnection of MOS transistors. In one application, the digitally ...


5
Mihai Banu, Alfred E Dunlop: Method and apparatus for clock recovery. AT&T Bell Laboratories, Jason Paul DeMont, August 17, 1993: US05237290 (25 worldwide citation)

A method and apparatus for recovering the phase of a signal which may change at periodic intervals is disclosed which comprises gated variable frequency oscillators. These results are obtained in an illustrative embodiment of the present invention in which an incoming signal is fed into a gated osci ...


6
Miron Abramovici, Alfred E Dunlop: Reconfigurable fabric for SoCs using functional I/O leads. Dafca, June 6, 2006: US07058918 (20 worldwide citation)

An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC ...


7
Alfred E Dunlop, Wilhelm C Fischer, Thaddeus J Gabara: Closed-loop frequency control of an oscillator circuit. AT&T, June 18, 1996: US05528199 (6 worldwide citation)

The output frequency of a simple low-power-dissipation oscillator circuit designed to drive PPS CMOS circuits is controlled by a closed-loop system. In response to deviations of the output frequency from a prescribed value, the system generates correction signals that are applied to an array of capa ...


8
William B Andrews, Alfred E Dunlop, John P Fishburn, Harold N Scholz: Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units. Lattice Semiconductor Corporation, November 26, 2002: US06486705 (4 worldwide citation)

Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution ...


9
Miron Abramovici, Alfred E Dunlop: Reconfigurable fabric for SoCs. Henry T Brendzel, October 28, 2004: US20040212393-A1

An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC ...


10
William B Andrews, Alfred E Dunlop, John P Fishburn, Harold N Scholz: Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units. Manelli Denison & Selter Pllc, January 10, 2002: US20020003445-A1

Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution ...