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Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie: Nonvolatile memory controller with error detection for concatenated error correction codes. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, December 31, 2013: US08621318 (49 worldwide citation)

A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been su ...


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Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie: Nonvolatile memory controller with concatenated error correction codes. PMC Sierra US, Kenneth Glass, Molly Sauter, Glass & Associates, February 18, 2014: US08656257 (28 worldwide citation)

A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using th ...


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Rino Micheloni, Luca Crippa, Alessia Marelli: Error correction code technique for improving read stress endurance. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, April 8, 2014: US08694855 (27 worldwide citation)

A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and gener ...


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Rino Micheloni, Alessia Marelli, Peter Z Onufryk: Shuffler error correction code system and method. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, April 8, 2014: US08694849 (25 worldwide citation)

A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one ...


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Rino Micheloni, Peter Z Onufryk, Alessia Marelli, Christopher I W Norrie: Nonvolatile memory controller with two-stage error correction technique for enhanced reliability. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, April 22, 2014: US08707122 (21 worldwide citation)

A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolat ...


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Rino Micheloni, Alessia Marelli, Christopher I W Norrie: High quality log likelihood ratios determined using two-index look-up table. Microsemi Storage Solutions, Glass and Associates, Kenneth Glass, September 20, 2016: US09450610 (6 worldwide citation)

A nonvolatile memory controller includes memory storage configured to store a two-index look-up table that includes a Log-Likelihood Ratio (LLR), hard-and-soft-decision bits associate with the LLR and a neighboring cell read pattern associated with the LLR. Read circuitry is configured to perform a ...


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Rino Micheloni, Peter Z Onufryk, Alessia Marelli, Christopher I W Norrie: Layer specific attenuation factor LDPC decoder. PMC Sierra US, Kenneth Glass, Molly Sauter, Glass & Associates, March 24, 2015: US08990661 (5 worldwide citation)

A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein a layer specific attenuation factor is provided for each layer of the LDPC parity check matrix. An attenuation factor matrix comprising a plurality of coefficients specifies the sp ...


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Rino Micheloni, Peter Z Onufryk, Alessia Marelli, Christopher I W Norrie, Ihab Jaser: Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values. PMC SIERRA US, Glass & Associates, Kenneth Glass, Mark Peloquin, September 8, 2015: US09128858 (5 worldwide citation)

Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A ...


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Rino Micheloni, Alessia Marelli, Peter Z Onufryk: System and method with reference voltage partitioning for low density parity check decoding. PMC SIERRA US, Kenneth Glass, Molly Sauter, Glass & Associates, January 12, 2016: US09235467 (5 worldwide citation)

A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the sm ...


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Rino Micheloni, Peter Z Onufryk, Alessia Marelli, Christopher I W Norrie: System and method for lifetime specific LDPC decoding. Microsemi Storage Solutions, Kenneth Glass, Mark Peloquin, Glass & Associates, July 19, 2016: US09397701 (4 worldwide citation)

A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory ...