1
Alberto J Reyes, Daniel J Snyder, Sleiman N Chamoun, Karen S Ramondetta: Method of selecting device threshold voltages for high speed and low power. Motorola, Rennie William Dover, June 30, 1998: US05774367 (156 worldwide citation)

A method of selecting device (14-16, 18-24, 28-30) threshold voltages for high speed and low overall power involves identifying (42) the critical paths by predetermined timing criteria. All transistors have an initial, typically high, threshold voltage (40). Transistors outside the critical paths ke ...


2
Alberto J Reyes, Steven D Millman, Sean C Tyler: Low power flip-flop circuit and method thereof. Motorola, Robert D Atkins, March 12, 1996: US05498988 (31 worldwide citation)

A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the ...


3
Alberto J Reyes, Gary K Yeap, James P Garvey: Method of generating power vectors for cell power dissipation simulation. Motorola, Robert D Atkins, Rennie William Dover, September 30, 1997: US05673420 (12 worldwide citation)

A method of generating power vectors to calculate power dissipation for a circuit cell is provided. The method involves formulating the Boolean equations (30) that describe the logical operation for a circuit cell (10). Primitive power vectors that cause an output to transition are generated (32) us ...


4
Dinesh D Gaitonde, Alberto J Reyes, Hongyu Xie, Dana M Rigg: Architectural power estimation method and apparatus. Motorola, Robert D Atkins, August 17, 1999: US05940779 (12 worldwide citation)

A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and the ...


5
Alberto J Reyes: System and method for correlated clock networks. Freescale Semiconductor, John A Fortkort, Margaret M Kelton, Fortkort Grether & Kelton, August 2, 2005: US06925622 (4 worldwide citation)

A clock network synthesis method and apparatus corrects for clock skew and impedance differences. A method includes identifying clock networks having more active elements as compared to other clock networks of a plurality of clock networks, for those identified clock networks, identifying a pattern ...


6
Alberto J Reyes: System and method for correlated clock networks. Motorola, Austin Intellectual Property, April 1, 2004: US20040064799-A1

A clock network synthesis method and apparatus corrects for clock skew and impedance differences. A method includes identifying clock networks having more active elements as compared to other clock networks of a plurality of clock networks, for those identified clock networks, identifying a pattern ...


7
Alberto J Reyes, Daniel J Sidar, Suleyman N Chamon, Karen S Raymonditta: Method of selecting high-speed-smallpower threshold voltage. Motorola, February 14, 1997: JP1997-045785

PROBLEM TO BE SOLVED: To provide a method of selecting threshold voltage of an element for maintaining a high-speed operation while reducing power consumption. SOLUTION: To begin with, a critical path is discriminated by a specified standard (42). All transistors have a high initial threshold voltag ...