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Rodney E Hooker, Colin Eddy, Darius D Gaskins, Albert J Loper Jr: Avoiding memory access latency by returning hit-modified when holding non-modified data. VIA Technologies, E Alan David, James W Huffman, January 29, 2013: US08364906

A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memor ...


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Rodney E Hooker, Colin Eddy, Darius D Gaskins, Albert J Loper JR: Avoiding memory access latency by returning hit-modified when holding non-modified data. Via Technologies, May 12, 2011: US20110113196-A1

A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memor ...


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John Michael Greer, Rodney E Hooker, Albert J Loper JR: Data prefetcher with multi-level table for predicting stride patterns. VIA Technologies, Huffman Law Group PC, January 13, 2011: US20110010506-A1

A data prefetcher includes a table of entries to maintain a history of load operations. Each entry stores a tag and a corresponding next stride. The tag comprises a concatenation of first and second strides. The next stride comprises the first stride. The first stride comprises a first cache line ad ...