1
John L Duncan, Albert J Loper Jr: Method and apparatus for optimizing dependent operand flow within a multiplier using recoding logic. Integrated Device Technology, James W Huffman, April 6, 1999: US05892699 (15 worldwide citation)

A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logi ...


2
Bryan Black, Marvin A Denman, Lee E Eisen, Robert T Golla, Albert J Loper Jr, Soummya Mallick, Russell A Reininger: Method and system for recoding noneffective instructions within a data processing system. International Business Machines Corporation, Michael A Davis Jr, Andrew J Dillon, April 8, 1997: US05619408 (14 worldwide citation)

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved ...


3
Dinesh K Jain, Albert J Loper Jr, Arturo Martin de Nicolas: Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide. IP First, Richard K Huffman, James W Huffman, May 9, 2000: US06061781 (14 worldwide citation)

An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequen ...


4
G Glenn Henry, Albert J Loper Jr, Terry Parks: Apparatus and method for absolute floating point register addressing. IP First L L C, Richard K Huffman, James W Huffman, October 17, 2000: US06134573 (6 worldwide citation)

An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as op ...


5
Daniel W J Johnson, Albert J Loper Jr: Apparatus and method for generating packed sum of absolute differences. VIA Technologies, E Alan Davis, James W Huffman, January 20, 2009: US07480685 (5 worldwide citation)

A microprocessor for generating a packed sum of absolute differences is disclosed. The microprocessor includes an instruction translator, for translating a Multimedia Extensions (MMX) Packed Sum of Absolute Differences Byte to Word (PSADBW) macroinstruction into at least first and second microinstru ...


6
Timothy A Elliott, G Glenn Henry, Albert J Loper Jr: Apparatus and method for improved floating point exchange. IP First, Richard K Huffman, James W Huffman, January 11, 2000: US06014736 (5 worldwide citation)

A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first ...


7
G Glenn Henry, Albert J Loper Jr: Method and apparatus for tracking coherence of dual floating point and MMX register files. IP First L L C, E Alan Davis, James W Huffman, May 7, 2002: US06385716 (4 worldwide citation)

An apparatus and method for tracking coherence between distinct floating point and MMX register files in a microprocessor is provided. The apparatus keeps track of the last time a floating point or MMX instruction was translated and what the instruction type of that previous instruction was by stori ...


8
Bryan Black, Marvin A Denman, Lee E Eisen, Robert T Golla, Albert J Loper Jr, Soummya Mallick, Russell Adley Reininger: Method and system for recording noneffective instructions within a data processing system. International Business Machines Corporation, Motorola, Mark E McBurney, Brian F Russell, Andrew J Dillon, February 10, 1998: US05717587 (2 worldwide citation)

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved ...


9
Albert J Loper Jr: Status register associated with MMX register file for tracking writes. IP First L L C, Mark J Danielson, James W Huffman, June 25, 2002: US06412065 (2 worldwide citation)

A portion of an x86 microprocessor that supports MMX instructions provides a write tracking unit that tracks writes to a separately provided MMX register file, and updates a status register accordingly. A write control unit uses the contents of the status register to control transfers between the MM ...


10
Albert J Loper Jr: Method and apparatus for selective writing of incoherent MMX registers. IP First L L C, George B F Yee, James W Huffman, January 15, 2002: US06339823 (2 worldwide citation)

A dual register file MMX-type architecture comprises monitoring logic for identifying which registers in a register file have been written to. The monitoring logic is coupled to write-enable logic associated with each register. Detection logic indicates the occurrence of an instruction boundary even ...