Akaogi Takao, Kawashima Hiromi, Takeguchi Tetsuji, Hagiwara Ryoji, Kasa Yasushi, Itano Kiyoshi, Ogawa Yasushige, Kawamura Shouichi: Flash memory improved in erasing characteristic, and circuit therefor.. Fujitsu, November 24, 1993: EP0570597-A1 (13 worldwide citation)

A flash memory improved in its erasing operation by shortening its erasing time, wherein, when data is written prior to erasing, by selecting a plurality of lines of at least either of word lines and bit lines simultaneously, data is written into a plurality of transistors in concurrence.

Akaogi Takao, Takashina Nobuaki, Kasa Yasushi, Itano Kiyoshi, Kawashima Hiromi, Yamashita Minoru, Kawamura Shouichi: Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.. Fujitsu, June 8, 1994: EP0600151-A2 (9 worldwide citation)

The device (particularly, a flash memory) has a first unit (101, 102, 120) for simultaneously selecting a block of 2 word lines among 2 word lines (n>m), and a second unit (101, 102, 120) for not selecting a block of 2 word lines among the 2 word lines (m>k). The second unit (101, 102, 120; 120, 130 ...

Kawashima Hiromi C O Fujitsu L, Akaogi Takao C O Fujitsu Limit: Nonvolatile semiconducteur memories.. Fujitsu, July 20, 1994: EP0606769-A2 (8 worldwide citation)

In a nonvolatile semiconductor memory, after a write or an erase operation, a read operation for verification is performed by applying a voltage at a first verification level (V2), which is lower than an applied voltage for a normal read operator, or a voltage at a second verification level (V3), wh ...

Akaogi Takao, Kawashima Hiromi: Semiconductor device having a fuse circuit and a detecting circuit for detecting the states of the fuses in the fuse circuit.. Fujitsu, January 13, 1988: EP0252325-A2 (8 worldwide citation)

A semiconductor device comprises a fuse circuit having first and second fuses (F1,F2) for storing an information by blown and unblown states of the fuses (F1,F2), an information output circuit for providing an output signal having a first logic level when at least one of the fuses (F1,F2) in blown a ...

Akaogi Takao: Electrically erasable, non-volatile semiconductor memory device for selective use in boot block type or normal type flash memory devices.. Fujitsu, April 13, 1994: EP0592069-A1 (7 worldwide citation)

An electrically erasable non-volatile semiconductor memory device has a memory cell array (1, 6), a first erase unit (4), a second erase unit (7), and an operation mode establish unit (9). The erasing operation of the second erase unit (7) is independently carried out of the erasing operation of the ...

Akaogi Takao: Semiconductor memory device.. Fujitsu, January 16, 1991: EP0408037-A2 (5 worldwide citation)

A semiconductor memory device comprises memory cells (34) for storing data, reference cells (44) for storing reference data, and an output part (5) supplied with an output signal from the memory cells and a reference signal from the reference cells for comparing the output signal and the reference s ...

Akaogi Takao: Signature circuit for non-volatile memory device.. Fujitsu, August 28, 1991: EP0443775-A2 (5 worldwide citation)

A signature circuit stores signature information indicative of one of a plurality of device functions of a non-volatile memory device which includes first memory cells (MS0-MS2m+1) which are respectively coupled to one of a plurality of word lines (X0-Xn) and to one of a plurality of bit lines (b0-b ...

Akaogi Takao: A programmable semiconductor memory apparatus.. Fujitsu, January 16, 1991: EP0408002-A2 (3 worldwide citation)

A programmable semiconductor memory apparatus comprises a memory cell array (1, 2, 3), a data sense circuit (4) for reading data from the memory cell array, and a bus line (Bu1,...) connected to a common node of a plurality of bit lines (B1, B2,...) forming the memory cell array and to the data sens ...

Takashina Nobuaki C O Fujitsu, Akaogi Takao C O Fujitsu Ltd: Non-volatile memory devices.. Fujitsu, May 15, 1991: EP0427260-A2 (3 worldwide citation)

A semiconductor non-volatile memory device, having a normal operating mode and a test mode, has bit lines (BL0, BL1, BLr), word lines (X0, X1, Xi) which intersect said bit lines, and a plurality of non-volatile memory cells (Q00, Q10, to Q1i) connected to the bit lines and word lines where the bit l ...

Akaogi Takao: Sense circuit for non-volatile memory device.. Fujitsu, August 28, 1991: EP0443776-A2 (3 worldwide citation)

A sense circuit for a non-volatile memory device includes a selecting circuit (Q5) for selecting a predetermined cell transistor by selecting a predetermined bit line (BL) which is connected to the predetermined cell transistor (Q6), a feedback type bias circuit (Q1, Q2, Q4) for maintaining a potent ...