1
Peter D MacWilliams, Robert L Farrell, Adalberto Golbert, Itzik Silas: Second level cache controller unit and system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 11, 1994: US05355467 (136 worldwide citation)

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus ...


2
Adalberto Golbert, Douglas M Carean, Roshan J Fernando, Amar A Ghori, Yoav Hochberg, Robert F Krick, Milind Mittal, Anurag Sah: Method and apparatus for operating a single CPU computer system as a multiprocessor system. Intel Corporation, Blakely Solkoloff Taylor & Zafman, February 6, 1996: US05490279 (24 worldwide citation)

A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus betwe ...


3
Amar A Ghori, Adalberto Golbert, Robert F Krick: Computer system having a central processing unit responsive to the identity of an upgrade processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 16, 1999: US05884091 (7 worldwide citation)

A uniprocessing computer system is provided with an original CPU and an upgrade socket for receiving an additional processor that need not be of a single predetermined type. On system RESET, the original CPU determines if an upgrade processor is resident in the upgrade socket and, if so, what kind o ...


4
Macwilliams Peter D, Farrell Robert L, Adalberto Golbert, Itzik Silas: Second level cache controller.. Intel, December 11, 1992: FR2677472-A1

Un système informatique comporte un cache secondaire pour accroître la capacité et la vitesse du système. Une mémoire cache secondaire (13) est prévue entre une unité centrale (10) comprenant un cache primaire et un bus de mémoire centrale (15). Un contrôleur de cache (12) est prévu en plus entre l' ...