1
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: High performance cost optimized memory with delayed memory writes. Rambus Incorporated, Intel Corporation, Pennie & Edmonds, June 13, 2000: US06075730 (134 worldwide citation)

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr ...


2
Ely K Tsern, Thomas J Holman, Richard M Barth, Andrew V Anderson, Paul G Davis, Craig E Hampel, Donald C Stark, Abhijit M Abhyankar: Memory device and system including a low power interface. Intel Corporation, Rambus, Pennie & Edmonds, April 23, 2002: US06378018 (113 worldwide citation)

A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power inte ...


3
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen: High performance cost optimized memory. Rambus Incorporated, Pennie & Edmonds, June 4, 2002: US06401167 (94 worldwide citation)

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals fro ...


4
Jared LeVan Zerbe, Michael Tak kei Ching, Abhijit M Abhyankar, Richard M Barth, Andy Peng Pui Chan, Paul G Davis, William F Stonecypher: Method and apparatus for fail-safe resynchronization with minimum latency. Rambus Incorporated, Pennie & Edmonds, October 29, 2002: US06473439 (65 worldwide citation)

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization ...


5
Frederick A Ware, Richard M Barth, Donald C Stark, Craig E Hampel, Ely K Tsern, Abhijit M Abhyankar, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: Apparatus and method for bus timing compensation. Rambus, Intel Corporation, Pennie & Edmonds, May 1, 2001: US06226757 (37 worldwide citation)

A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bu ...


6
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen: High performance cost optimized memory. Rambus, Morgan Lewis & Bockius, March 15, 2005: US06868474 (34 worldwide citation)

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals fro ...


7
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen: Integrated circuit memory device having write latency function. Rambus, Morgan Lewis & Bockius, March 27, 2007: US07197611 (32 worldwide citation)

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals fro ...


8
Scott C Best, Abhijit M Abhyankar, Kun Yung Chang, Frank Lambrecht: Drift tracking feedback for communication channels. Rambus, Mark A Haynes, Haynes Beffel & Wolfeld, November 1, 2005: US06961862 (29 worldwide citation)

A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operatio ...


9
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen: Integrated circuit memory device with delayed write command processing. Rambus, Morgan Lewis & Bockius, October 23, 2007: US07287119 (26 worldwide citation)

An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed b ...


10
Jared LeVan Zerbe, Michael Tak kei Ching, Abhijit M Abhyankar, Richard M Barth, Andy Peng Pui Chan, Paul G Davis, William F Stonecypher: Phase comparator capable of tolerating a non-50% duty-cycle clocks. Rambus, Morgan Lewis & Bockius, September 27, 2005: US06949958 (23 worldwide citation)

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization ...