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David T Hass, Abbas Rashid: Advanced processor with interrupt delivery mechanism for multi-threaded multi-CPU system on a chip. Ipsg PC, February 10, 2005: US20050033889-A1

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...


32
Abbas Rashid, David T Hass: Advanced processor with interfacing messaging network to a CPU. Ipsg PC, February 24, 2005: US20050044308-A1

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...


33
Abbas Rashid, David T Hass: Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads. Ipsg PC, February 24, 2005: US20050044324-A1

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...


34
David T Hass, Abbas Rashid: Advanced processor with mechanism for fast packet queuing operations. Ipsg PC, February 24, 2005: US20050041651-A1

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...


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Jerome F Duluk, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Dorsey & Whitney, July 8, 2004: US20040130552-A1

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


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Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner: Cross-bar switch incorporating a sink port with retry capability. Juniper Networks, Shumaker & Sieffert P A, April 26, 2007: US20070091880-A1

A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted on the Retry input, the sink port a ...


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Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner: Cross-bar switch having bandwidth allocation. Juniper Networks, Shumaker & Sieffert P A, June 7, 2007: US20070127469-A1

A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multi ...


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Jerome F Duluk, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hung, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, Apple Computer, c o DORSEY & WHITNEY, July 19, 2007: US20070165035-A1

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


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Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Anh Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory G Spurrier, Sankar Ramanoorthi, Michael Freed: Content service aggregation system. Juniper Networks, Shumaker & Sieffert Pa, May 15, 2008: US20080114887-A1

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Proto ...


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David T Hass, Abbas Rashid: Advanced processor with system on a chip interconnect technology. Zilka Kotab PC, May 29, 2008: US20080126709-A1

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...