1
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, R Michael Ananian, Dorsey & Whitney, April 6, 2004: US06717576 (151 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphic ...


2
Jerome F Duluk Jr, Richard E Hessel, Joseph P Grass, Abbas Rashid, Bo Hong, Abraham Mammen: Method and apparatus for generating texture. Apple Computer, Flehr Hohbach Test Albritton & Herbert, September 11, 2001: US06288730 (101 worldwide citation)

A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of det ...


3
Abbas Rashid, Nazar Zaidi: Cross-bar switch employing a multiple entry point FIFO. Juniper Networks, Shumaker & Sieffert P A, February 27, 2007: US07184446 (93 worldwide citation)

A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports coupled to the input ports to accept and forward the data packets. Each sink port includes a multiple entry point FIFO with multiple data inputs for receiving data packets. In one implementation, the ...


4
Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Anh Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory G Spurrier, Sankar Ramanoorthi, Michael Freed: Content service aggregation system. Juniper Networks, Shumaker & Sieffert P A, December 4, 2007: US07305492 (77 worldwide citation)

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Proto ...


5
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, Dorsey & Whitney, January 23, 2007: US07167181 (68 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


6
Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Ahn Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory G Spurrier, Sankar Ramanoorthi, Michael Freed: Content service aggregation system. Juniper Networks, Shumaker & Sieffert P A, July 27, 2010: US07765328 (63 worldwide citation)

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Proto ...


7
David T Hass, Abbas Rashid: Advanced processor with system on a chip interconnect technology. RMI Corporation, Zilka Kotab PC, February 19, 2008: US07334086 (54 worldwide citation)

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...


8
Abbas Rashid, David T Hass: Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip. RMI Corporation, Zilka Kotab PC, December 16, 2008: US07467243 (25 worldwide citation)

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...


9
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Yo, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple, Dorsey & Whitney, October 5, 2010: US07808503 (19 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


10
David T Hass, Abbas Rashid: Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages. RMI Corporation, Zilka Kotab PC, December 1, 2009: US07627717 (19 worldwide citation)

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...