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Belgacem Haba Belgacem (Bel) Haba
Joseph Fjelstad, Masud Beroz, John W Smith, Belgacem Haba: Microelectronic packages having deformed bonded leads and methods therefor. Lerner David Littenberg Krumholz & Mentlik, June 6, 2002: US20020068426-A1 (1 worldwide citation)

A method of making a microelectronic assembly includes juxtaposing a first element, such as a dielectric sheet having conductive leads thereon with a second element, such as a semiconductor chip, having contact thereon, and wire bonding the conductive leads on the first element to the contacts on th ...


2
Eugene Fitzgerald
Eugene A Fitzgerald, Richard Hammond, Matthew Currie: Gate technology for strained surface channel and strained buried channel MOSFET devices. Samuels Gauthier & Stevens, June 6, 2002: US20020068393-A1

A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectri ...


3
Steven Teig, Joseph L Ganley: Method and apparatus for placing circuit modules. Stattler Johansen & Adeli, June 6, 2002: US20020069397-A1 (5 worldwide citation)

Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the delay cost of a placement configuration by accounting for the potential use of diagonal wiring in the layout. Some of thes ...


4
King Tsu Jae: Negative differential resistance field effect transistor (NDR-FET) & circuits using the same. J Nicholas Gross Attorney at Law, June 6, 2002: US20020066933-A1 (5 worldwide citation)

An improved negative differential resistance field effect transistor (NDR-FET) is disclosed. The NDR FET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be op ...


5
King Tsu Jae: Charge pump for negative differential resistance transistor. J Nicholas Gross Attorney at Law, June 6, 2002: US20020067651-A1 (5 worldwide citation)

An integrated circuit device includes a charge pump for providing a bias signal to a field effect transistor (FET) that is capable of operating in a negative differential resistance mode. The bias signal is applied to a gate of the NDR FET to control the characteristics of the NDR behavior.


6
Peter A Goode, Andrew Gould, Alan Christie, Charles E Vise: Well having a self-contained inter vention system. Schlumberger Reservoir Completions, June 6, 2002: US20020066556-A1 (5 worldwide citation)

A system includes a subsea well and a carousel of tools. The carousel of tools is adapted to automatically and selectively deploy the tools in the well to perform an intervention in the well. The flow of fluid in a well is halted, and a tool is deployed from within the well while the fluid is halted ...


7
Linda M Braun, William Robert Holland, Jane D LeGrange: Variable optical delay lines and methods for making same. Glen E Books Esq, Lowenstein Sandler PC, June 6, 2002: US20020067877-A1 (4 worldwide citation)

In accordance with the invention, a high-resolution variable optical delay line comprises an optical switch, such as an optical micromechanical mirror switch, and an array of delay fiber paths. Each delay fiber path in the array comprises a region where the fiber is curved differently from the other ...


8
Avner Karpol, Silviu Reinhorn, Emanuel Elysaf, Shimon Yalov, Boaz Kenan: Method of and apparatus for article inspection including speckle reduction. Applied Materials, Sughrue Mion Pllc, June 6, 2002: US20020067478-A1 (3 worldwide citation)

A method and apparatus for reducing speckle during inspection of articles used in the manufacture of semiconductor devices, including wafers, masks, photomasks, and reticles. The coherence of a light beam output by a coherent light source, such as a pulsed laser, is reduced by disposing elements in ...


9
Warren M Farnworth: Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages. Trask Britt, June 6, 2002: US20020066966-A1 (3 worldwide citation)

A stereolithographically fabricated package that surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. The package may be fabricated from thermoplastic glass, other types of glass, ceramics, or metals. Stereolithographic processes are used to fabricat ...


10
Ts O Paul O P, Duff Robert, Deamond Scott: Conjugates of glycosylated/galactosylated peptide. Cell Works, Johns Hopkins University, Ts O Paul O P, Duff Robert, Deamond Scott, LARCHER Carol, June 6, 2002: WO/2002/043771 (3 worldwide citation)

A conjugate of formula A-L-P, in which: A represents a glycosylated/galactosylated peptide that binds to a cell-surface receptor, L represents a bifunctional linker, which does not comprise a naturally occurring amino acid and is covalently bonded to A and P in a regiospecific manner, and P represen ...



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