1
Rajan Suresh, Smith Michael, Wang David: Methods and apparatus of stacking drams. Metaram, Rajan Suresh, Smith Michael, Wang David, ZILKA Kevin J, March 8, 2007: WO/2007/028109 (71 worldwide citation)

Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


2
Dixon Christopher J, Pinckney Thomas: Indicating website reputations within search results. Mcafee, Dixon Christopher J, Pinckney Thomas, ZILKA Kevin J, November 9, 2006: WO/2006/119481 (50 worldwide citation)

An aspect of the present invention relates to methods and systems involving presenting a plurality of search results within a graphical user interface, and presenting an indicia of reputation in association with at least one of the plurality of search results within the search results graphical user ...


3
Slavenburg Gerrit A, Fox Thomas F, Cook David R: System, method, and computer program product for controlling stereo glasses shutters. Nvidia Corporation, Slavenburg Gerrit A, Fox Thomas F, Cook David R, ZILKA Kevin J, November 8, 2007: WO/2007/126904 (37 worldwide citation)

A system, method, and computer program product are provided for controlling stereo glasses shutters. In use, a right eye shutter of stereo glasses is controlled to switch between a closed orientation and an open orientation, by utilizing a right eye control signal (206). Further, a left eye shutter ...


4
Rajan Suresh Natarajan, Schakel Keith R, Smith Michael John Sebastian, Wang David T, Weber Frederick Daniel: Memory circuit system and method. Metaram, Rajan Suresh Natarajan, Schakel Keith R, Smith Michael John Sebastian, Wang David T, Weber Frederick Daniel, ZILKA Kevin J, May 29, 2008: WO/2008/063251 (10 worldwide citation)

A memory circuit system (Figure 1) and method are provided in the context of various embodiments. In one embodiment, an interface circuit (102) remains in communication with a plurality of memory circuits (104) and a system. The interface circuit is operable to interface the memory circuits and the ...


5
Danilak Radoslav: Delaying an operation that reduces a lifetime of memory. Sandforce, Danilak Radoslav, ZILKA Kevin J, May 29, 2008: WO/2008/063647 (9 worldwide citation)

A system, method, and computer program product are provided for delaying operations that reduce a lifetime of memory. In use, at least one aspect associated with a lifetime of memory is identified. To this end, at least one operation that reduces the lifetime of the memory is delayed, based on the a ...


6
Dixon Christopher J, Pinckney Thomas: Determining website reputations using automatic testing. Mcafee, Dixon Christopher J, Pinckney Thomas, ZILKA Kevin J, November 9, 2006: WO/2006/119479 (8 worldwide citation)

An aspect of the present invention relates to methods and systems involving automatically generating a third party assessment of a website's reputation, and storing an indicia of the assessment in a format and location that may be accessible by a client computing facility attempting to interact with ...


7
Greene Mark, Hegarty Michael, Cantwell Dermot: Voice control of a media player. Voicedemand, Greene Mark, Hegarty Michael, Cantwell Dermot, ZILKA Kevin J, January 18, 2007: WO/2007/008248 (6 worldwide citation)

A media player system, method and computer program product are provided. In use, an utterance is received. A command for a media player is then generated based on the utterance. Such command is utilized for providing wireless control of the media player.


8
Hass David T, Kuila Kaushik, Shahid Ahmed, Garg Gaurav: System and method for parsing and allocating a plurality of packets to processor core threads. Rmi Corporation, Hass David T, Kuila Kaushik, Shahid Ahmed, Garg Gaurav, ZILKA Kevin J, August 13, 2009: WO/2009/099573 (6 worldwide citation)

An apparatus and method are provided for allocating a plurality of packets to different processor threads. In operation, a plurality of packets are parsed to gather packet information. Additionally, a parse operation is performed utilizing the packet information to generate a key, and a hash algorit ...


9
Zhu Julianne Jiang, Hass David T: Delegating network processor operations to star topology serial bus interfaces. Rmi Corporation, Zhu Julianne Jiang, Hass David T, ZILKA Kevin J, February 5, 2009: WO/2009/017668 (5 worldwide citation)

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of th ...


10
Laker Robert William, Hass David T, Kuila Kaushik: System and method for compression processing within a compression engine. Rmi Corporation, Laker Robert William, Hass David T, Kuila Kaushik, ZILKA Kevin J, January 8, 2009: WO/2009/005758 (4 worldwide citation)

An apparatus to implement a deflate process in a compression engine. An embodiment of the apparatus includes a hash table, a dictionary, comparison logic, and encoding logic. The hash table is configured to hash a plurality of characters of an input data stream to provide a hash address. The diction ...



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