1
David L Wood, Paul Weschler, Derk Norton, Chris Ferris, Yvonne Wilson, William R Soley: Log-on service providing credential level change without loss of session continuity. Sun Microsystems, Zagorin O&apos Brien & Graham, August 19, 2003: US06609198 (372 worldwide citation)

A security architecture has been developed in which a single sign-on is provided for multiple information resources. Rather than specifying a single authentication scheme for all information resources, the security architecture associates trust-level requirements with information resources. Authenti ...


2
David L Wood, Derk Norton: Access management system and method employing secure credentials. Sun Microsystems, Zagorin O&apos Brien & Graham, December 23, 2003: US06668322 (308 worldwide citation)

A security architecture has been developed in which a single sign-on is provided. Session credentials are used to maintain continuity of a persistent session across multiple accesses to one or more information resources, and in some embodiments, across credential level changes. Session credentials a ...


3
Juan Carlos Martinez Guerra, Tina L Timmerman, Katherine G Hammer, David H Marshall: Parser translator system and method. Evolutionary Technologies International, Zagorin O&apos Brien & Graham, February 18, 2003: US06523172 (254 worldwide citation)

A parser-translator technology allows a user to specify complex test and/or transformation statements in a high-level user language, to ensure that such test and/or transformation statements are well-formed in accordance with a grammar defining legal statements in the user language, and to translate ...


4
David L Wood, Thomas Pratt, Michael B Dilger, Derk Norton, Yunas Nadiadi: Security architecture with environment sensitive credential sufficiency evaluation. Sun Microsystems, Zagorin O&apos Brien & Graham L, February 10, 2004: US06691232 (253 worldwide citation)

By including environment information in a security policy, a security architecture advantageously allows temporal, locational, connection type and/or client capabilities-related information to affect the sufficiency of a given credential type (and associated authentication scheme) for access to a pa ...


5
Daniel Mann: Processor having a trace access instruction to access on-chip trace memory. Advanced Micro Devices, Zagorin O&apos Brien & Graham, November 6, 2001: US06314530 (187 worldwide citation)

A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory ...


6
Bendik Kleveland, Roy E Scheuerlein, N Johan Knall, Mark G Johnson, Thomas H Lee: Three-dimensional memory array incorporating serial chain diode stack. Matrix Semiconductor, Zagorin O&apos Brien & Graham L, October 7, 2003: US06631085 (140 worldwide citation)

A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same di ...


7
Robert J Proebsting: Programmable and electrically configurable latch timing circuit. Integrated Device Technology, Zagorin O&apos Brien & Graham, October 8, 2002: US06462998 (113 worldwide citation)

Integrated circuits incorporating latching sense amplifier circuits usually provide substantial latch timing margins. Excess latch timing margins may be reduced by using a latch timing circuit for controlling the timing of a latch enable signal which is both programmable and electrically configurabl ...


8
Robert J Proebsting: Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD. Zagorin O&apos Brien & Graham, April 16, 2002: US06373753 (85 worldwide citation)

A high performance dynamic memory array architecture is disclosed in several embodiments. The row decoders drive the selected word line to a boosted VPP voltage that is internally generated by a charge pump type circuit whose output is a substantially fixed voltage which is regulated with respect to ...


9
Guy L Steele Jr, Alexander T Garthwaite, Paul A Martin, Nir N Shavit, Mark S Moir, David L Detlefs: Lock-free implementation of concurrent shared object with dynamic node allocation and distinguishing pointer value. Sun Microsystems, Zagorin O&apos Brien & Graham, November 30, 2004: US06826757 (79 worldwide citation)

A novel linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, non-blocking completion of access operations is achieved without restric ...


10
Mark G Johnson, Thomas H Lee, Vivek Subramanian, Paul Michael Farmwald, James M Cleeves: Integrated circuit structure including three-dimensional memory array. Matrix Semiconductor, Zagorin O&apos Brien & Graham, May 7, 2002: US06385074 (79 worldwide citation)

An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit ...



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