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Katherina Babich
Katherina E Babich, Scott D Halle, David V Horak, Arpan P Mahorowala, Wesley C Natzle, Dirk Pfeiffer, Hongwen Yan: Etch selectivity enhancement for tunable etch resistant anti-reflective layer. International Business Machines Corporation, Yuanmin Cai Esq, Hoffman Warnick & D Alessandro, July 18, 2006: US07077903 (4 worldwide citation)

Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA laye ...


2
Christopher B D Aleo, Gregory M Johnson, Muthukumarasamy Karthikeyan, Shenzhi Yang, Balasingham Bahierathan: Via chains for defect localization. International Business Machines Corporation, STMicroelectronics, Gibb & Riley, Yuanmin Cai Esq, October 1, 2013: US08546155 (44 worldwide citation)

Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geomet ...


3
Wai Kin Li, Haining S Yang: Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques. International Business Machines Corporation, Gibb I P Law Firm, Yuanmin Cai Esq, December 27, 2011: US08083958 (41 worldwide citation)

Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combin ...


4
Mukta G Farooq, Ian D Melville, Kevin S Petrarca: Soft error rate mitigation by interconnect structure. International Business Machines Corporation, Gibb I P Law Firm, Yuanmin Cai Esq, February 21, 2012: US08120175 (14 worldwide citation)

A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the ...


5
Anil K Chinthakindi: High capacitance density vertical natural capacitors. International Business Machines Corporation, Gibb & Rahman, Yuanmin Cai Esq, December 16, 2008: US07466534 (10 worldwide citation)

Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomp ...


6
Xiangdong Chen, Geng Wang, Da Zhang: Method and structure to improve body effect and junction capacitance. International Business Machines Corporation, Freescale Semiconductor, Gibb & Riley, Yuanmin Cai Esq, October 30, 2012: US08299545 (10 worldwide citation)

A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to fo ...


7
Nathaniel C Berliner, Pranita Kulkarni, Nicolas Loubet, Kingsuk Maitra, Sanjay C Mehta, Paul A Ronsheim, Toyoji Yamamoto, Zhengmao Zhu: Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion. International Business Machines Corporation, Globalfoundries, Renesas Electronics America, STMicroelectronics, Gibb & Riley, Yuanmin Cai Esq, December 2, 2014: US08900973 (8 worldwide citation)

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the ...


8
Anil K Chinthakindi: High capacitance density vertical natural capacitors. International Business Machines Corporation, Gibb I P Law Firm, Yuanmin Cai Esq, January 11, 2011: US07866015 (7 worldwide citation)

Disclosed are embodiments of a method of forming a capacitor with inter-digitated vertical plates such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back ...


9
Xiangdong Chen, Jong Ho Lee, Weipeng Li, Dae Gyu Park, Kenneth J Stein, Voon Yew Thean: Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors. International Business Machines Corporation, Gibb I P Law Firm, Yuanmin Cai Esq, January 11, 2011: US07867839 (7 worldwide citation)

Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both ...


10
Xiangdong Chen, Young G Ko, Haining Yang: Selective stress engineering for SRAM stability improvement. International Business Machines Corporation, Samsung Electronics, Scully Scott Murphy & Presser P c, Yuanmin Cai Esq, June 17, 2008: US07388267 (7 worldwide citation)

An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intent ...