1
Ronald Bove, Eric M Hubacher: High density wafer contacting and test system. International Business Machines Corporation, Wesley DeBruin, July 26, 1977: US04038599 (192 worldwide citation)

A contactor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a sem ...


2
Lawrence E Forget, Robert A Gdula, Joseph C Hollis: Selective reactive ion etching of polysilicon against SiO.sub.2 utilizing SF.sub.6 -Cl.sub.2 -inert gas etchant. International Business Machines Corporation, Wesley DeBruin, July 29, 1980: US04214946 (158 worldwide citation)

Disclosed is an improved Reactive Ion Etch (RIE) technique for etching polysilicon or single crystal silicon as must be done in Very Large Scale Integration (VLSI) using silicon technology. It teaches the use of an etch gas that consists of a mixture of sulfur hexafluoride (SF.sub.6) and chlorine (C ...


3
Erich Berndlmaier, Bernard T Clark, Jack A Dorler: Heat transfer structure for integrated circuit package. International Business Machines Corporation, Wesley DeBruin, April 6, 1982: US04323914 (147 worldwide citation)

Heat is removed from a Large Scale Integrated Circuit semiconductor package via a thermal conductive path including a thermally conductive liquid. The integrated circuit chips are flip chip bonded to a substrate having a printed circuit and raised contact pads serving to interconnect contact areas o ...


4
George Anthony Caccoma, Paul Philip Castrucci, William Otto Druschel: Automated integrated circuit manufacturing system. International Business Machines Corporation, Wesley DeBruin, May 31, 1977: US04027246 (137 worldwide citation)

A computer controlled manufacturing system employing random access semiconductor wafer storage in the fabrication of integrated circuit devices.


5
Robert G Meeker, William J Scanlon, Zvi Segal: Gas encapsulated cooling module. International Business Machines Corporation, Wesley DeBruin, February 6, 1979: US04138692 (77 worldwide citation)

A gas encapsulated cooling module wherein at least one semiconductor chip to be cooled is supported on a substrate portion of the module the provision of a heat sink stud having a planar surface in thermal contact with a planar surface of the chip to be cooled, said stud being supported by a resilie ...


6
Robert M Morton, Ariel L Perlmann: Programmable interface contactor structure. International Business Machines Corporation, Wesley DeBruin, June 15, 1976: US03963986 (77 worldwide citation)

A programmable interface contactor structure including a plurality of discrete electrical probes geometrically arranged, or oriented, to respectively electrically contact a discrete one of an array of conductive pads on a device under test. The plurality of discrete probes are contained and supporte ...


7
Johann Hajdu, Guenter Knauft: LSI Circuitry conforming to level sensitive scan design (LSSD) rules and method of testing same. International Business Machines Corporation, Wesley DeBruin, November 3, 1981: US04298980 (61 worldwide citation)

An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each ...


8
Maurice T McMahon: Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection. International Business Machines Corporation, Wesley DeBruin, April 3, 1984: US04441075 (60 worldwide citation)

Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic ...


9
Sumit DasGupta, Matthew C Graf, Robert A Rasmussen, Thomas W Williams: Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks. International Business Machines Corporation, Wesley DeBruin, March 5, 1985: US04503386 (57 worldwide citation)

Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density pac ...


10
Reginald F Lever, John L Mauer IV, Alwin E Michel, Laura B Rothman: Planar deep oxide isolation process utilizing resin glass and E-beam exposure. International Business Machines Corporation, Wesley DeBruin, September 16, 1980: US04222792 (57 worldwide citation)

A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate, said process comprising the steps: