1
Michael D Muth, Keith R Spencer: Mirror assembly. K W Muth Company, Wells St John Roberts Gregory & Matkin PS, August 4, 1998: US05788357 (328 worldwide citation)

A mirror assembly including a semitransparent mirror which passes about 1% to about 8% of a broad band of visible light, and which reflects about 35% to about 58% of a broad band of visible light. A light assembly is positioned adjacent to the semitransparent mirror and emits visible light which is ...


2
Gurtej S Sandhu, Trung Tri Doan: System for real-time control of semiconductor wafer polishing. Micron Technology, Wells St John Roberts Gregory & Matkin PS, July 17, 2001: US06261151 (76 worldwide citation)

A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head sel ...


3
Mark Jost, Charles H Dennison, Kunal Parekh: Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells. Micron Technology, Wells St John Roberts Gregory & Matkin PS, October 8, 1996: US05563089 (56 worldwide citation)

A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with on ...


4
Michael A Dieter: Disposable expandable speculum. Wells St John Roberts Gregory & Matkin PS, February 10, 1998: US05716329 (54 worldwide citation)

An expandable speculum is described which may be provided in kit form. The speculum includes a handle with an integral eyepiece. A set of first elongated tubular members, each releasably connectable to the handle adjacent the eyepiece are formed of a substantially rigid material. Each includes an ex ...


5
Wen Li: Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal. Micron Technology, Wells St John Roberts Gregory & Matkin PS, May 29, 2001: US06240042 (30 worldwide citation)

A method and apparatus for synchronizing output data and data strobe signals uses internal interleaved clock signals in a double data rate (DDR) DRAM that are synchronized with an external clock. A delay-locked loop internal to the DDR DRAM is locked to an external clock signal and generates the int ...


6
Jon R Williamson, Edward Nowak, Emmanuel de Muizon: Protection circuits and methods of protecting a semiconductor device. VLSI Technology, Wells St John Roberts Gregory & Matkin PS, July 18, 2000: US06091594 (18 worldwide citation)

Protection circuits and methods of protecting a semiconductor device are provided. According to one aspect, the present invention provides a protection circuit adapted to be coupled to a ground connection, pad and power bus of a semiconductor device, the protection circuit includes electrically coup ...


7
William Mish: Wireless communication devices and methods of forming wireless communication devices. Micron Technology, Wells St John Roberts Gregory & Matkin PS, July 3, 2001: US06254006 (17 worldwide citation)

Wireless communication devices and methods of forming the same are described. In one implementation, an integrated circuitry transceiver chip and an antenna are operably coupled and mounted within a housing member. A cover(s) is (are) disposed over the chip and antenna and effectively seals the chip ...


8
John T Moore: Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry. Wells St John Roberts Gregory & Matkin Ps, February 6, 2003: US20030027416-A1 (17 worldwide citation)

A method of forming memory circuitry sequentially includes forming a plurality of metal interconnect lines over a semiconductive substrate. A plurality of memory cell storage devices comprising voltage or current controlled resistance setable semiconductive material are then formed. In one implement ...


9
John T Moore, Terry L Gilton: Chalcogenide comprising device. Wells St John Roberts Gregory & Matkin Ps, January 2, 2003: US20030001229-A1 (16 worldwide citation)

A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of t ...


10
Luan Tran, Alan R Reinberg: Methods of forming integrated circuitry, and methods of forming dynamic random access memory circuitry. Micron Technology, Wells St John Roberts Gregory & Matkin PS, October 2, 2001: US06297129 (14 worldwide citation)

Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cell ...