1
Victor Chan, Kathryn W Guarini, Meikei Ieong: Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers. International Business Machines Corporation, Wan Yee Cheung Esq, Scully Scott Murphy & Presser, November 23, 2004: US06821826 (151 worldwide citation)

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D ...


2
Charles T Black, Kathryn Wilder Guarini: Nonvolatile memory device using semiconductor nanocrystals and method of forming same. International Business Machines Corporation, Wan Yee Cheung Esq, McGinn IP Law Group PLLC, May 16, 2006: US07045851 (118 worldwide citation)

A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-asse ...


3
Hussein I Hanafi, Robert H Dennard, Wilfried E Haensch: Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Wan Yee Cheung Esq, August 8, 2006: US07089515 (110 worldwide citation)

A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the ...


4
Qiqing Christine Ouyang, Xiangdong Chen: High mobility heterojunction complementary field effect transistors and methods thereof. International Business Machines Corporation, George Sai Halasz, Wan Yee Cheung, June 6, 2006: US07057216 (107 worldwide citation)

In all representative embodiments presented, the Ge concentration in the source and drain 10 and the SiGe epitaxial channel layer 20 is in the 15% to 50% range, preferably between about 20% to 40%. The SiGe thicknesses in the source/drain 10 are staying below the critical thickness for the given Ge ...


5
Hussein I Hanafi, Diane C Boyd, Kevin K Chan, Wesley Natzle, Leathen Shi: Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region. International Business Machines Corporation, Wan Yee Cheung, Scully Scott Murphy & Presser, December 9, 2003: US06660598 (82 worldwide citation)

A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an S ...


6
Meikei Ieong, Alexander Reznicek, Min Yang: CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Wan Yee Cheung Esq, April 4, 2006: US07023055 (77 worldwide citation)

A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the meth ...


7
Hussein I Hanafi, Jeffrey J Brown, Wesley C Natzle: Damascene double-gate MOSFET with vertical channel regions. International Business Machines Corporation, Wan Yee Cheung Esq, Scully Scott Murphy & Presser, December 28, 2004: US06835614 (74 worldwide citation)

A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fab ...


8
Kevin K Chan, Meikei Ieong, Alexander Reznicek, Devendra K Sadana, Leathen Shi, Min Yang: Strained silicon CMOS on hybrid crystal orientations. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Wan Yee Cheung et al, August 8, 2006: US07087965 (71 worldwide citation)

Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or ...


9
Meikei Ieong, Min Yang: Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Wan Yee Cheung Esq, August 29, 2006: US07098508 (70 worldwide citation)

The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconduct ...


10
Meikei Ieong, Min Yang: Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations. International Business Machines Corporation, Wan Yee Cheung, Scully Scott Murphy & Presser, November 9, 2004: US06815278 (68 worldwide citation)

The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconduct ...