1
Cliff Wood Jr, David K Ovard, George E Pax, John R Tuttle: Method and apparatus for remote monitoring. Micron Technology, Walter D Fields, April 13, 1999: US05894266 (147 worldwide citation)

A remote intelligent communications device includes a primary RF communications port and an alternative modem communications port. The remote intelligent communications device receives configuration data for configuring the alternative modem communications port. The remote intelligent communications ...


2
Daniel A Koos, Sung C Kim, Gurtej S Sandhu: Method of chemical mechanical polishing. Micron Technology, Walter D Fields, August 10, 1999: US05934980 (138 worldwide citation)

A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. ...


3
Daniel A Koos, Sung C Kim, Gurtej S Sandhu: Method of chemical mechanical polishing. Micron Technology, Walter D Fields, May 22, 2001: US06234877 (95 worldwide citation)

A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. ...


4
Gurtej S Sandhu, Richard L Elliott, Trung T Doan, Jody D Larsen: IC mechanical planarization process incorporating two slurry compositions for faster material removal times. Micron Technology, Walter D Fields, November 30, 1999: US05994224 (88 worldwide citation)

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chem ...


5
Gurtej S Sandhu, Richard L Elliott, Trung T Doan, Jody D Larsen: IC mechanical planarization process incorporating two slurry compositions for faster material removal times. Micron Technology, Walter D Fields, March 21, 2000: US06040245 (88 worldwide citation)

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a CMP process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chem ...


6
Michael D Nelson: Mezzanine integrated circuit interconnect. Xilinx, Walter D Fields, Edel M Young, Justin Liu, August 23, 2005: US06932618 (31 worldwide citation)

An interconnect assembly to electrically interconnect one or more integrated circuits to an electronic device may comprise a base package to couple to a circuit board of the electronic device. A terminal mezzanine package may support the integrated circuit(s) above the base package. A first set of c ...


7
Warren E Cory, Joseph Neil Kryzak: Variable latency buffer and method of operation. XILINX, Walter D Fields, W Eric Webostad, April 14, 2009: US07519747 (28 worldwide citation)

A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read point ...


8
Pierre C Fazan, Martin C Roberts, Gurtej S Sandhu: Spacers used to form isolation trenches with improved corners. Micron Technology, Walter D Fields, March 31, 1998: US05733383 (26 worldwide citation)

A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate ...


9
Andrew E Horch, Fred Hause: Thyrister semiconductor device. T RAM, Walter D Fields, May 3, 2005: US06888176 (25 worldwide citation)

In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, s ...


10
Vishnu K Agarwal: Electrode and capacitor structure for a semiconductor device and associated methods of manufacture. Micron Technology, Walter D Fields, April 17, 2001: US06218256 (24 worldwide citation)

An electrode and capacitor structure, and methods of manufacture thereof, are disclosed for a semiconductor device. The capacitor includes a dielectric layer sandwiched between opposing first and second electrically conductive electrodes. At least one of the electrodes includes a thin, oxygen-anneal ...