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Eb Eshun
Ebenezer Eshun: Structure and method for integrating front end SiCr resistors in HiK metal gate technologies. Texas Instruments Incorporated, Jacqueline J Garner, Wade J Brady III, Frederick J Telecky Jr, March 25, 2014: US08680618 (4 worldwide citation)

An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resi ...


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Russell M Kinder, Marco Corsi: Dual buck-boost converter with single inductor. Texas Instruments Incorporated, Wade J Brady III, Frederick J Telecky Jr, October 2, 2007: US07276886 (113 worldwide citation)

A dual output buck-boost power converter operates with a single inductor to achieve high efficiency with automatic or inherent load balancing. Switches associated with the opposite polarity outputs are driven based on feedback signals, with one feedback signal being a reference voltage and another f ...


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Franz Prexl, Erich Bayer, Juergen Neuhaeusler: Buck-boost DC/DC converter with overlap control using ramp shift signal. Texas Instruments Deutschland, John J Patti, Wade J Brady III, Frederick J Telecky Jr, April 14, 2009: US07518346 (108 worldwide citation)

A buck-boost DC/DC converter includes an inductor and a power stage having a set of switches selectively connecting the inductor between a voltage input, a voltage output and a reference level in accordance with buck or boost mode. The converter has a switch control providing control signals to the ...


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Per Torstein Roine: Technique for memory imprint reliability improvement. Texas Instruments Incorporated, Rose Alyssa Keagy, Wade J Brady III, Frederick J Telecky Jr, July 23, 2013: US08495438 (104 worldwide citation)

One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents a ...


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Jeffrey A Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E Howard: Advanced CMOS using super steep retrograde wells. Texas Instruments Incorporated, Jacqueline J Garner, Wade J Brady III, Frederick J Telecky Jr, February 8, 2011: US07883977 (104 worldwide citation)

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent ...


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Jeffrey A Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E Howard: Advanced CMOS using super steep retrograde wells. Texas Instruments Incorporated, Jacqueline J Garner, Wade J Brady III, Frederick J Telecky Jr, February 2, 2010: US07655523 (103 worldwide citation)

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent ...


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Jeffrey A Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E Howard: Advanced CMOS using super steep retrograde wells. Texas Instruments Incorporated, Wade J Brady III, Frederick J Telecky Jr, March 10, 2009: US07501324 (102 worldwide citation)

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent ...


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Jeffrey A Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E Howard: Advanced CMOS using super steep retrograde wells. Texas Instruments Incorporated, Jacqueline J Garner, Wade J Brady III, Frederick J Telecky Jr, March 6, 2012: US08129246 (102 worldwide citation)

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent ...


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Puneet Kohli, Manoj Mehrotra: Multiple indium implant methods and devices and integrated circuits therefrom. Texas Instruments Incorporated, Warren L Franz, Wade J Brady III, Frederick J Telecky Jr, June 14, 2011: US07960238 (102 worldwide citation)

An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor su ...


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