1
Burn Jeng Lin: Apparatus for method for immersion lithography. Taiwan SEmiconductor Manufacturing, Tung & Associates, September 7, 2004: US06788477 (287 worldwide citation)

An apparatus for immersion lithography that includes an imaging lens which has a front surface, a wafer that has a top surface to be exposed positioned spaced-apart and juxtaposed to the front surface of the imaging lens, and a fluid that has a refractive index between about 1.0 and about 2.0 fillin ...


2
Shinn Sheng Yu: Optical proximity correction common process window maximization over varying feature pitch. Taiwan Semiconductor Manufacturing, Tung & Associates, June 15, 2004: US06749972 (171 worldwide citation)

Maximizing a common process window for optical proximity correction (OPC)-modified features of a semiconductor design having varying pitch is disclosed. For each pitch within a semiconductor design, a bias needed at the pitch that maximizes a common process window for the number of pitches given a c ...


3
Lain Jong Li, Yung Cheng Lu, Chung Chi Ko: Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer. Taiwan Semiconductor Manufacturing, Tung & Associates, August 5, 2003: US06602779 (151 worldwide citation)

Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a hard mask layer formed upon the dielectric layer. The hard mask layer i ...


4
Tsing Chow Wang, Te Sung Wu, Erh Kong Chieh: Method for fabricating a microelectronic fabrication having formed therein a redistribution structure. Aptos Corporation, Tung & Associates, March 26, 2002: US06362087 (145 worldwide citation)

Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate and in electrical communication with the patterned bond pad layer a patterned redistribution ...


5
Yee Chia Yeo, Fu Liang Yang, Chenming Hu: Strained-channel multiple-gate transistor. Taiwan Semiconductor Manufacturing, Tung & Associates, February 15, 2005: US06855990 (144 worldwide citation)

A multiple-gate semiconductor structure is disclosed which includes a substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces. The fin is subjected to a strain of at least 0.01% and is positioned vertically on the substrate; source and drain regions for ...


6
Ling Chen Kung, Jyh Rong Lin, Kuo Chuan Chen: Wafer level packaging method and packages formed. Industrial Technology Research Institute, Tung & Associates, August 21, 2001: US06277669 (125 worldwide citation)

A method for fabricating a wafer level package and packages formed are disclosed. In the method, an elastomeric material layer is first deposited on top of a passivation layer by a printing, coating or laminating method to form a plurality of isolated islands. The islands may have a thickness of les ...


7
Li Jui Chen, Ran Jin Lin: Fabry-Perot filter apparatus with enhanced optical discrimination. Industrial Technology Research Institute, Tung & Associates, July 27, 2004: US06768555 (115 worldwide citation)

Within a Fabry-Perot filter apparatus, a method for fabricating the Fabry-Perot filter apparatus and a method for operating the Fabry-Perot filter apparatus, there is employed a Fabry-Perot filter and at least one color filter layer, both assembled over a substrate and covering at least two optical ...


8
Luen Chian Sun: Probing of device elements. Taiwan Semiconductor Manufacturing, Tung & Associates, June 7, 2005: US06902941 (100 worldwide citation)

A new and improved method for the probing of integrated circuits (ICs) and is particularly suitable for probing various elements of an IC for failure analysis or other electrical testing and/or measurement of the IC. The method includes providing a probe access trench in the IMD (intermetal dielectr ...


9
Yai Yei Huang, Yuh Da Fan: Method of removing metal etching residues following a metal etchback process to improve a CMP process. Taiwan Semiconductor Manufacturing, Tung & Associates, August 30, 2005: US06936544 (99 worldwide citation)

A method for reducing wafer surface scratching in a metal CMP process including providing a semiconductor wafer having a process surface comprising a blanket deposited metal layer; dry etching in an etchback process comprising a fluorine containing etching chemistry to remove at least a portion of t ...


10
Min Hwa Chi, Wen Chuan Chiang, Mu Chi Chiang: Quasi-plannar and FinFET-like transistors on bulk silicon. Taiwan Semiconductor Manufacturing, Tung & Associates, July 21, 2009: US07564105 (98 worldwide citation)

The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A second device has a doped, recessed channel and has a plurality of edge-fins juxtaposed on an edge of an ...



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