1
John Moore: Apparatus and method for dual cell common electrode PCRAM memory device. Thomas J D Amico, Dickstein Shapiro Morin & Oshinsky, February 27, 2003: US20030038301-A1 (13 worldwide citation)

Two PCRAM cells which use a common anode between them are disclosed. The two memory cells can be accessed separately to store two bits of data which can be read and written, and can be stacked one over the other with a common anode between them to form an upper and lower cell pair. Respective access ...


2
Terry L Gilton, Kristy A Campbell: Method of retaining memory state in a programmable conductor RAM. Thomas J D Amico, Dickstein Shapiro Morin & Oshinsky, March 6, 2003: US20030043631-A1 (12 worldwide citation)

A non-volatile memory device, such as a Programmable Conductor Random Access Memory (PCRAM) device, having an exemplary memory stored state retention characteristic is disclosed. There is provided a method for retaining stored states in a random access memory device generally comprising the steps of ...


3
John T Moore, Joseph F Brooks: Electrode structure for use in an integrated circuit. Micron Technology, Thomas J D Amico, Dickstein Shapiro Morin & Oshinsky, May 22, 2003: US20030096497-A1 (12 worldwide citation)

An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed ...


4
Wendell P Noble, Leonard Forbes: High density vertical sram cell using bipolar latchup induced by gated diode breakdown. Thomas J D Amico, Dickstein Shapiro Morin & Oshinsky, September 27, 2001: US20010024841-A1 (6 worldwide citation)

Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells an ...


5
Sungkwon C Hong: Imaging with gate controlled charge storage. Aptina Imaging Corporation, Thomas J D Amico, December 29, 2009: US07638825 (5 worldwide citation)

A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obtain efficient charge transfer and l ...


6
Timothy J Allen: Removable heat sink bumpers on a quad flat package. Thomas J D Amico, Dickstein Shapiro Morin & Oshinsky, October 11, 2001: US20010028553-A1 (1 worldwide citation)

A heat sink for a quad flat package comprises a heat-radiating plate and a plurality of removable bumpers attached to the plate. An area of reduced thickness is disposed at the junction between each bumper and the plate to facilitate removal of the plurality of bumpers from the plate. Preferably, ea ...


7
Howard E Rhodes: Method for forming a low leakage contact in a cmos imager. Thomas J D Amico, Dickstein Shapiro Morin & Oshinsky, January 31, 2002: US20020011614-A1 (1 worldwide citation)

An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region i ...


8
Alexander Krymski: Differential readout from pixels in CMOS sensor. Dickstein Shapiro Morin & Oshinsky, Thomas J D Amico, March 18, 2004: US20040051802-A1 (1 worldwide citation)

The present invention provides an improved pixel readout circuit that compensates for common mode noise during a read out operation. This is accomplished by using a differential readout of the signal and reset value from the desired pixel compared with the reset value from a reference pixel. In this ...


9
Howard E Rhodes, Werner Juengling, Thomas A Figura, Steven D Cummings: Optimized low leakage diodes, including photodiodes. Dickstein Shapiro Morin & Oshinsky, Thomas J D Amico, August 30, 2001: US20010017382-A1 (1 worldwide citation)

A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes accor ...


10
Howard E Rhodes: Trench isolation for semiconductor devices. Thomas J D Amico Esq, Dickstein Shapiro Morin & Oshinsky, August 16, 2001: US20010013631-A1 (1 worldwide citation)

A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in r ...