61
Alain Artieri: Programmed memory with improved speed and power consumption. STMicroelectronics, Theodore E Galanthay, Lisa K Jorgenson, August 17, 1999: US05940332 (46 worldwide citation)

A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array that has a ...


62
Jacob Riseman: Method of forming an integrated circuit structure with fully-enclosed air isolation. International Business Machines Corporation, Theodore E Galanthay, September 25, 1979: US04169000 (46 worldwide citation)

A method for forming a fully-enclosed air isolation structure which comprises etching a pattern of cavities extending from one surface of a silicon substrate into the substrate to laterally surround and electrically isolate said plurality of substrate pockets, and then forming a first layer of silic ...


63
Christopher S Lam: Memory sharing architecture for a decoding in a computer system. STMicroelectronics, David V Carlson, Theodore E Galanthay, Lisa K Jorgenson, September 28, 1999: US05960464 (46 worldwide citation)

A method and apparatus employing a memory management system that can be used with applications requiring a large contiguous block of memory, such as video decompression techniques (e.g., MPEG 2 decoding). The system operates with a computer and the computer's operating system to request and employ a ...


64
David C McClure, Thomas A Teel: Circuit for providing a compensated bias voltage. SGS Thomson Microelectronics, Rodney M Anderson, Theodore E Galanthay, Renee M Larson, October 22, 1996: US05568084 (45 worldwide citation)

A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating tra ...


65
David C McClure: Method and apparatus for programming signal timing. SGS Thomson Microelectronics, Theodore E Galanthay, Kenneth C Hill, Lisa K Jorgenson, November 26, 1996: US05579326 (44 worldwide citation)

A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational spe ...


66
Leslie Vajtay: End caps for tubular containers. Theodore E Galanthay, October 19, 1976: US03986659 (44 worldwide citation)

Disclosed is a rigid end plug snugly inserted into a tube formed from plastic sheet material. The tube has perforations near its open ends into which axially tapered radial protrusions from the end plug are inserted. The end plug has a beveled edge for ease of snug insertion into the tube and a rim ...


67
David C McClure: Circuit and method for setting the time duration of a write to a memory cell. STMicroelectronics, David V Carlson, Theodore E Galanthay, Lisa K Jorgenson, December 21, 1999: US06006339 (43 worldwide citation)

A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. The write simu ...


68
Andrea Ghilardelli, Jacopo Mulatti, Stefano Ghezzi: Positive charge pump. SGS Thomson Microelectronics S r l, James H Morris, Theodore E Galanthay, Wolf Greenfield & Sacks P C, June 13, 2000: US06075402 (43 worldwide citation)

A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS trans ...


69
David C McClure: Fault detection for entire wafer stress test. SGS Thomson Microelectronics, Theodore E Galanthay, Lisa K Jorgenson, Irena Lager, April 8, 1997: US05619462 (43 worldwide citation)

A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. On each die, a test mode control circuit, having a first and a second test mode control inputs, and a test enable circuit, having a first and a second test enable ...


70
Ardeshir Jehangir Sidhwa, Stephen John Melosky: Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation pump down step. STMicroelectronics, Theodore E Galanthay, Lisa K Jorgenson, Daniel E Venglarik, July 24, 2001: US06265312 (43 worldwide citation)

A tungsten film stack is formed on a wafer using a deposition chamber by first depositing a nucleation on the wafer in the presence of a carrier gas, such as nitrogen. Following deposition of the nucleation, excess carrier gas is evacuated from the deposition chamber. Then, following evacuation of t ...