1
Richard P Pashby, Douglas W Phelps Jr, Sigvart J Samuelsen, William C Ward: Package semiconductor chip. International Business Machines Corporation, Francis J Thornton, Theodore E Galanthay, Michael J Weins, August 29, 1989: US04862245 (453 worldwide citation)

The present invention is directed to a packaged semiconductor chip which effectively dissipates heat and has improved performance. The packaged chip has a plurality of lead frame conductors extending through the encapsulating material which are adhesively joined to the semiconductor chip, preferably ...


2
Pierangelo Magni: Plastic package for electronic devices. SGS Thomson Microelectronics S r l, James H Morris, Theodore E Galanthay, Wolf Greenfield & Sacks P C, August 28, 2001: US06281566 (163 worldwide citation)

A semiconductor electronic device comprises a chip of a semiconductor material, a set of metal conductors adjacent to the plate, a set of wire leads joining selected points on the chip to the metal conductors, and a supporting metal plate formed of three portions having a total surface area which is ...


3
Robert H Bond, Michael J Hundt: Ball-grid-array integrated circuit package with solder-connected thermal conductor. SGS Thomson Microelectronics, Theodore E Galanthay, Lisa K Jorgenson, June 24, 1997: US05642261 (149 worldwide citation)

An integrated circuit package with a path of high thermal conductivity is disclosed. The package is formed into a substrate, such as a printed circuit board or a ceramic substrate, through which an opening has been formed to receive a thermally conductive slug, formed of a material such as copper. A ...


4
Michel Marty, Herve Jaouen: Transformer for integrated circuits. STMicroelectronics, Theodore E Galanthay, David V Seed and Berry Carlson, February 29, 2000: US06031445 (121 worldwide citation)

A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting ...


5
Javathu K Hassan, Alfred Mack, Michael R Wojtaszek: Method and apparatus for handling workpieces. International Business Machines Corporation, Frank C Leach Jr, Theodore E Galanthay, July 13, 1976: US03968885 (120 worldwide citation)

A semiconductor wafer, which has chips formed thereon, is moved from a class 100 environment into a vacuum chamber in which pattern writing is performed on the chips by an electron beam without significantly affecting the vacuum level in the vacuum chamber. The wafer is initially disposed on an elev ...


6
James Brady: Method and apparatus for accessing a memory device. STMicroelectronics, Theodore E Galanthay, Lisa K Jorgenson, Andre Szuwalski, December 5, 2000: US06157578 (113 worldwide citation)

A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration cir ...


7
Massimo Mancuso: Non-linear image filter for filtering noise. STMicroelectronics, David V Carlson, Theodore E Galanthay, Lisa K Jorgenson, August 22, 2000: US06108455 (112 worldwide citation)

A system and method for reducing noise using recursive noise level estimation. The system and method for noise reduction substitute a target pixel in a processing window with a weighted average of a plurality of neighboring pixels according to the degree of similarity between thc target pixel and th ...


8
Richard J Ferrant: Dynamic random access memory device with a latching mechanism that permits hidden refresh operations. STMicroelectronics, Theodore E Galanthay, Lisa K Jorgenson, Peter J Thoma, December 21, 1999: US06005818 (112 worldwide citation)

A dynamic access memory (DRAM) device includes a plurality of memory cells for storing data signals. The DRAM device has a row decoding mechanism that allows selected memory cells to be accessed upon receipt of a row address signal during a read operation and a write operation. A latching mechanism ...


9
Raul Zegers Diaz, Jefferson Eugene Owen: Video and/or audio decompression and/or compression device that shares a memory interface. STMicroelectronics, David V Carlson, Theodore E Galanthay, Lisa K Jorgenson, September 22, 1998: US05812789 (105 worldwide citation)

An electronic system that contains a first device that requires a memory interface and video and/or audio decompression and/or compression device that shares a memory interface and memory with the first device while still permitting the video and/or audio decompression and/or compression device to o ...


10
Anthony Fung, Peter Groz, Jim C Hsu, Danny K Hui, Harry S Hvostov: Transaction interface for a data communication system. STMicroelectronics, David V Carlson, Theodore E Galanthay, Lisa K Jorgenson, June 5, 2001: US06243778 (103 worldwide citation)

A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The t ...