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Eugene Fitzgerald
Matthew Currie, Anthony Lochtefeld, Richard Hammond, Eugene Fitzgerald: Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same. AmberWave Systems Corporation, Testa Hurwitz & Thibeault, December 14, 2004: US06831292 (259 worldwide citation)

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are pre ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Buried channel strained silicon FET using a supply layer created through ion implantation. AmberWave Systems Corporation, Testa Hurwitz & Thibeault, April 29, 2003: US06555839 (133 worldwide citation)

A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or buried channel MOSFETS. In another exemplary embod ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Buried channel strained silicon FET using a supply layer created through ion implantation. Amberwave Systems Corporation, Testa Hurwitz & Thibeault, July 15, 2003: US06593191 (82 worldwide citation)

A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe ca ...


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Eugene Fitzgerald
Eugene A Fitzgerald, Nicole Gerrish: Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS. AmberWave Systems Corporation, Testa Hurwitz & Thibeault, April 19, 2005: US06881632 (64 worldwide citation)

A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of sai ...


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Eugene Fitzgerald
Kenneth C Wu, Eugene A Fitzgerald, Jeffrey T Borenstein: Etch stop layer system. Massachusetts Institute of Technology, Testa Hurwitz & Thibeault, February 18, 2003: US06521041 (61 worldwide citation)

A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si


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