1
Joseph Andrew Iadanza: System and method for dynamically reconfiguring a programmable gate array. International Business Machines Corporation, Susan M Murray Esq, Heslin & Rothenberg P C, July 8, 1997: US05646544 (309 worldwide citation)

In each of multiple logic cells of a Programmable Gate Array ("PGA"), a programing array is provided having multiple programming words therein. Each of the programming words is engagable to control the configuration of the logic cell. The programming words are selectively engaged such that multiple ...


2
Kim P N Clinton, Scott W Gould, Steven P Hartman, Joseph A Iadanza, Frank R Keyser III, Eric E Millham: Programmable array interconnect network. International Business Machines Corporation, Susan M Murray Esq, Heslin & Rothenberg P C, May 20, 1997: US05631578 (146 worldwide citation)

A programmable interconnection system for a programmable array includes pluralities of parallel buses for rows and columns of logic cells arranged in the array. Two groups of seven buses are provided for each row or column of logic cells. The buses include conductors connectable to each other, and s ...


3
Timothy A Brunner, Louis L Hsu, Jack A Mandelman, Li Kong Wang: High performance multi-mesa field effect transistor. International Business Machines Corporation, Susan M Murray Esq, Whitham Curtis Whitham & McGinn, October 7, 1997: US05675164 (73 worldwide citation)

A high performance transistor includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Mesa structures are formed at sub-lithographic size and pitch as recesses ...


4
Scott Whitney Gould, Frederick Curtis Furtek, Frank Ray Keyser III, Brian A Worth, Terrance John Zittritsch: Programmable array clock/reset resource. International Business Machines Corporation, Atmel Corporation, Susan M Murray Esq, Heslin & Rothenberg P C, July 29, 1997: US05652529 (73 worldwide citation)

A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a ...


5
Allan Robert Bertolet, Kim P N Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A Worth, Gulson Yasar, Terrance John Zittritsch: Programmable logic cell having configurable gates and multiplexers. International Business Machines Corporation, Susan M Murray Esq, Heslin & Rothenberg P C, July 8, 1997: US05646546 (33 worldwide citation)

A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates recei ...


6
Joseph Andrew Iadanza: Programmable circuits for test and operation of programmable gate arrays. International Business Machines Corporation, Susan M Murray Esq, Heslin & Rothenberg P C, July 22, 1997: US05651013 (19 worldwide citation)

A system for scan testing a programmable array of logic cells is provided. The storage circuits of the logic cells are converted into master/slave storage circuits and connected into a shift register for scan testing. The storage circuits require A, B and C clocks during operation. A programmable cl ...


7
Michael D Armacost, David Dobuzinsky, Jeffrey Gambino, Son Nguyen: High density selective SiO.sub.2 :Si.sub.3 N.sub.4 etching using a stoichiometrically altered nitride etch stop. International Business Machines Corporation, Susan M Murray Esq, Whitham Curtis Whitham & McGinn, April 22, 1997: US05622596 (17 worldwide citation)

Selectivity of SiO.sub.2 to Si.sub.3 N.sub.4 is increased with the additional of silicon rich nitride conformal layer to manufacturing of semiconductor chip. Silicon rich nitride conformal layer may be used in place of or in addition to standard nitride conformal layers in manufacture.


8
Vincent James McGahay, James Gardner Ryan, Michael Jay Shapiro, Christopher Joseph Waskiewicz: Method and apparatus for determining chamber cleaning end point. International Business Machines Corporation, Susan M Murray Esq, Michael J Balconi Lamica Esq Jenkens & Gilchrist P C, January 27, 1998: US05712702 (15 worldwide citation)

A marker element is included in a deposition chamber. After use of the chamber to deposit films or coatings on workpieces, the chamber is cleaned to remove materials which may contaminate future processing of workpieces in the chamber. The composition of the gas exhausted from the chamber during the ...


9
Takeshi Asano, Shinichi Ikami: Data transfer system interconnecting a computer and a display device. International Business Machines Corporation, Susan M Murray Esq, July 14, 1998: US05781742 (5 worldwide citation)

Disclosed is a data transfer system that effectively reduces EMI radiation, in a device wherein EMI radiation very easily occurs, without the need for filters, etc. A system for transmitting data across a bus having a plurality of data lines includes a modulating circuit for modulating data so as to ...