61
Juergen Brendel: World-wide-web server that finds optimal path by sending multiple syn+ack packets to a single client. Resonate, Stuart T Auvinen, July 1, 2003: US06587438 (63 worldwide citation)

An optimal path through the Internet to a client is determined by the server during connection establishment. During the 3-way handshake that establishes a connection, a web server ordinarily sends a single SYN+ACK packet to the client. Instead of sending just one SYN+ACK packet, the serve ...


62
Juergen Brendel: Virtualizing network-attached-storage (NAS) with a compact table that stores lossy hashes of file names and parent handles rather than full names. Sandbox Networks, g Patent, Stuart T Auvinen, September 18, 2007: US07272654 (60 worldwide citation)

Multiple Network Attached Storage (NAS) appliances are pooled together by a virtual NAS translator, forming one common name space visible to clients. Clients send messages to the virtual NAS translator with a file name and a virtual handle of the parent directory that are concatenated to a full file ...


63
Charles C Lee, I Kang Yu, Edward W Lee, Ming Shiang Shen: Flash-memory card for caching a hard disk drive with data-area toggling of pointers stored in a RAM lookup table. Super Talent Electronics, Stuart T Auvinen, gPatent, October 27, 2009: US07610438 (60 worldwide citation)

A flash-memory cache card caches data that a host writes to a hard disk drive. A flash-memory array has physical blocks of flash memory arranged into first and second data areas having M blocks each, and a wear-leveling-counter pool. An incoming logical sector address (LSA) from a host is mapped to ...


64
James S Blomgren, Cheryl Senter Brashears: Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor. Exponential Technology, Stuart T Auvinen, March 16, 1999: US05884057 (60 worldwide citation)

A processor that can execute both CISC and RISC instructions has an integer pipeline and a floating point pipeline. RISC instructions are sent to the floating point pipeline at the beginning of the integer pipeline, but CISC instructions re-align the floating point pipeline. CISC instructions are se ...


65
David Q Chow, Frank Yu, Charles C Lee, Abraham C Ma, Ming Shiang Shen: Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear. Super Talent Electronics, Stuart T Auvinen, gPatent, January 31, 2012: US08108590 (59 worldwide citation)

A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is wri ...


66
James S Blomgren, Earl T Cohen, Brian R Baird: Block-based branch prediction using a target finder array storing target sub-addresses. Exponential Technology, Stuart T Auvinen, March 4, 1997: US05608886 (57 worldwide citation)

A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch instruction is in, or if the target address is in the next or previous 2K-byte block. The upper portion ...


67
Tao Lin: 3D triangle rendering by texture hardware and color software using simultaneous triangle-walking and interpolation for parallel operation. NeoMagic, Stuart T Auvinen, January 18, 2000: US06016151 (55 worldwide citation)

A 3D graphics accelerator operates in parallel with a host central processing unit (CPU). Software executing on the host CPU performs transformation and lighting operations on 3D-object primitives such as triangles, and generates gradients across the triangle for red, green, blue, Z-depth, alpha, fo ...


68
David E Richter, James S Blomgren: Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register. Exponential Technology, Stuart T Auvinen, September 2, 1997: US05664159 (55 worldwide citation)

A single breakpoint address register on a CPU is shared to emulate a plurality of breakpoint registers. A plurality of breakpoints are stored in an emulation area of main memory. One of these breakpoints is loaded into the single breakpoint register on the CPU. When a translation-lookaside buffer (T ...


69
David E Richter, Earl T Cohen, James S Blomgren: Emulation of segment bounds checking using paging with sub-page validity. Exponential Technology, Stuart T Auvinen, August 8, 1995: US05440710 (55 worldwide citation)

Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is achieved by ext ...


70
Tao Lin, Vincent Chor Fung Yu, Tianhua Tang, Beong Kwon Hwang: Merged pipeline for color interpolation and edge enhancement of digital images. Neomagic, Stuart T Auvinen, November 4, 2003: US06642962 (55 worldwide citation)

A digital-camera processor receives mono-color digital pixels from an image sensor. Each mono-color pixel is red, blue, or green. The stream of pixels from the sensor has alternating green and red pixels on odd lines, and blue and green pixels on even lines in a Bayer pattern. Each mono-color pixel ...