51
Horng Yee Chou, Ben Wei Chen: Serial interface to flash-memory chip using PCI-express-like packets and packed data for partial-page writes. Super Talent Electronics, gPatent, Stuart T Auvinen, October 31, 2006: US07130958 (70 worldwide citation)

A serial flash-memory chip has a serial-bus interface to an external controller. A flash-memory block in the serial flash-memory chip can be read by the external controller sending a read-request packet over the serial bus to the serial flash-memory chip, which reads the flash memory and sends the d ...


52
Dan Schonfeld, Karthik Hariharakrishnan, Philippe Raffy, Fathy Yassa: Occlusion/disocclusion detection using K-means clustering near object boundary with comparison of average motion of clusters to object and background motions. NeoMagic, Stuart T Auvinen, November 28, 2006: US07142600 (69 worldwide citation)

An object in a video sequence is tracked by object masks generated for frames in the sequence. Macroblocks are motion compensated to predict the new object mask. Large differences between the next frame and the current frame detect suspect regions that may be obscured in the next frame. The motion v ...


53
Hung Sung Li: Precise, low-jitter fractional divider using counter of rotating clock phases. NeoMagic, Stuart T Auvinen, October 19, 1999: US05970110 (69 worldwide citation)

A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock incr ...


54
Ben Wei Chen, Horng Yee Chou, Sun Teck See: USB smart switch with packet re-ordering for interleaving among multiple flash-memory endpoints aggregated as a single virtual USB endpoint. Super Talent Electronics, Stuart T Auvinen, July 4, 2006: US07073010 (68 worldwide citation)

A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host ...


55
Earl T Cohen, Russell W Tilleman, Jay C Pattin, James S Blomgren: Master-slave cache system for instruction and data cache memories. Exponential Technology, Stuart T Auvinen, August 27, 1996: US05551001 (68 worldwide citation)

A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline of a processor, and a slave data cache for supplying data operands to an execution pipeline of the proces ...


56
Tao Lin: Audio sample-rate conversion using a linear-interpolation stage with a multi-tap low-pass filter requiring reduced coefficient storage. NeoMagic, Stuart T Auvinen, May 25, 1999: US05907295 (68 worldwide citation)

Audio sample rates are converted by an arbitrary ratio of Q/P using a two-stage sample-rate converter. One stage is an L-tap low-pass finite-impulse-response (FIR) filter, while the other stage is a linear interpolator. Coefficient storage for the L-tap low-pass FIR filter is dramatically reduced by ...


57
James S Blomgren, David E Richter, Cheryl Senter Brashears: Shared floating-point registers and register port-pairing in a dual-architecture CPU. Exponential Technology, Stuart T Auvinen, November 4, 1997: US05685009 (67 worldwide citation)

A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC program to a RISC ...


58
Andrew Rosman, Ming Ju Li: Multiple triangle pixel-pipelines with span-range pixel interlock for processing separate non-overlapping triangles for superscalar 3D graphics engine. Neomagic, Stuart T Auvinen, April 24, 2001: US06222550 (66 worldwide citation)

A 3D graphics processor has parallel triangle pixel pipelines. One or more triangle setup engine(s) receives triangle primitives from a host or geometry engine and generates vertex color, texture and other attributes as well as their gradients. The triangle setup engine makes available all required ...


59
Ramon S Co, David Sun: Repairing Advanced-Memory Buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module. Kingston Technology, Stuart T Auvinen, g Patent, January 6, 2009: US07474576 (65 worldwide citation)

A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. ...


60
Ravi V Condamoor, Ankur Datta Sharma, Neelakantan Sundaresan: Net-value creation and allocation in an electronic trading system. Neha Net, Stuart T Auvinen, February 21, 2006: US07003486 (63 worldwide citation)

An electronic exchange creates and distributes value among trading partners in a trade. Trading agents for the trading partners use a value manager to store true values for a trading element in the trade. The true values are the values perceived by the trading partner, but are not shown to other tra ...