31
Matthew P Freivald, Mark S Richards, Alan C Noble: Checksum-comparing change-detection tool indicating degree and location of change of internet documents. NetMind Technologies, Stuart T Auvinen, April 17, 2001: US06219818 (113 worldwide citation)

A change-detection web server automatically checks web-page documents for recent changes. The server retrieves and compares documents one or more times a week. The user is notified by electronic mail when a change is detected. The user registers a web-page document by submitting his e-mail address a ...


32
Guozhu Long, Anthony J P O Toole: Time-multiplexed transmission on digital-subscriber lines synchronized to existing TCM-ISDN for reduced cross-talk. Centillium Technology, Stuart T Auvinen, November 23, 1999: US05991311 (111 worldwide citation)

Pulp-insulated telephone cables common in Japan and other countries have higher cross-talk interference than plastic-insulated cables common in the United States. Deployment of newer xDSL systems in Japan has been limited by the high cross-talk interference in those pulp cables, especially the near- ...


33
Hung Cao Nguyen, Son Hong Ho: DVD controller with embedded DRAM for ECC-block buffering. NeoMagic, Stuart T Auvinen, December 26, 2000: US06167551 (109 worldwide citation)

An embedded DRAM is incorporated inside a digital-versatile-disk (DVD) playback-controller integrated circuit. Data from the DVD optical disk is written to a data block in the embedded DRAM. Error correction is performed by reading the data block to generate syndromes and over-writing errors in the ...


34
Jay C Pattin, James S Blomgren: Multi-processor DRAM controller that prioritizes row-miss requests to stale banks. Exponential Technology, Stuart T Auvinen, April 28, 1998: US05745913 (106 worldwide citation)

Memory requests from multiple processors are re-ordered to maximize DRAM row hits and minimize row misses. Requests are loaded into a request queue and simultaneously decoded to determine the DRAM bank of the request. The last row address of the decoded DRAM bank is compared to the row address of th ...


35
Earl T Cohen, James S Blomgren, David E Richter: Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU. Exponential Technology, Stuart T Auvinen, July 14, 1998: US05781457 (100 worldwide citation)

A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a ...


36
Horng Yee Chou, Ren Kang Chiou, Ben Wei Chen: Dual-personality extended-USB plug and receptacle with PCI-Express or Serial-At-Attachment extensions. Super Talent Electronics, Stuart T Auvinen, April 4, 2006: US07021971 (98 worldwide citation)

An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plu ...


37
James S Blomgren, David E Richter: Dual-instruction-set architecture CPU with hidden software emulation mode. Exponential Technology, Stuart T Auvinen, July 14, 1998: US05781750 (97 worldwide citation)

A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code. Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode. Emulation mode is entered upon reset, and p ...


38
James S Blomgren, David E Richter: Shared register architecture for a dual-instruction-set CPU. Exponential Technology, Stuart T Auvinen, January 2, 1996: US05481693 (97 worldwide citation)

A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC program to a RISC p ...


39
Deepraj S Puar: Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad. NeoMagic, Stuart T Auvinen, April 9, 1996: US05506499 (92 worldwide citation)

Each touchdown of a probe card during wafer-sort testing of integrated circuits can leave a gouge in the pad metal. These gouges reduce the reliability of any wire bond to that pad as voids can be left in the bond where the gouges are. A second auxiliary test pad is adjacent to the primary bonding p ...


40
James S Blomgren: Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order. Exponential Technology, Stuart T Auvinen, July 30, 1996: US05542059 (88 worldwide citation)

A CPU pipeline is able to process instructions from a complex instruction set computer CISC instruction set and from a reduced instruction set computer RISC set. A mode register is provided to indicate whether RISC or CISC instructions are currently being processed. Two instruction decode units are ...