A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...
A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are ...
A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second cont ...
A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second cont ...
A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in e ...
A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are ...
A semiconductor package and a method for fabricating the package are provided. The package includes multiple substrates in a stacked configuration, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing side ...
A method for forming contact pins adapted to form an electrical connection with a mating contact location is provided. In a first embodiment, the contact pins are formed on an interconnect used for testing a semiconductor die and are adapted to establish an electrical connection with the bond pads o ...
A method and apparatus for chemically mechanically planarizing (CMP) a semiconductor wafer includes directing acoustic waves at the wafer and receiving reflected acoustic waves from the wafer during the (CMP) process. By analyzing the acoustic waves and reflected acoustic waves a thickness of the wa ...
A method and apparatus for mechanical planarization and endpoint detection of a semiconductor wafer or the like. The apparatus includes a polishing head for rotating the wafer under a controlled pressure against a rotating polishing platen. The polishing head is mounted such that the wafer can be mo ...
