1
Eliezer Pasternak, Gideon Ben Efraim, Stuart M Feeney: Wireless ATM metropolitan area network. Netro Corporation, Alan H MacPherson, Fabio E Marino, Skjerven Morrill MacPherson Franklin and Friel, August 10, 1999: US05936949 (231 worldwide citation)

The present invention provides an efficient point-to-multipoint microwave ATM network including a base station (BS) broadcasting a continuous transmission with a sector antenna. The system uses time division multiplex (TDM) for downstream transmission and time division multiple access (TDMA) for ups ...


2
Won Sun Shin, Byung Joon Han, Ju Hoon Yoon, Sung Bum Kwak, In Gyu Han: Lead end grid array semiconductor package. Anam Semiconductor, Amkor Technology, Thomas S MacDonald, Skjerven Morrill MacPherson Franklin and Friel, February 2, 1999: US05866939 (225 worldwide citation)

The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length forming a lead end grid array semiconductor package. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part and/or at lea ...


3
Richard K Williams, Mohammad Kasem: Vertical power mosfet having thick metal layer to reduce distributed resistance. Siliconix Incorporated, David E Steuber, Skjerven Morrill MacPherson Franklin and Friel, September 9, 1997: US05665996 (221 worldwide citation)

The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly ...


4
Frank M Dunlap, Hock C So, Sau C Wong: Feedback loop for reading threshold voltage. Invox Technology, David T Millers, Skjerven Morrill MacPherson Franklin and Friel, May 5, 1998: US05748534 (146 worldwide citation)

To read the threshold voltage of a transistor such as a floating gate transistor in an analog or multi-level memory cell, the transistor is connected in a feedback loop which contains a differential amplifier having an output terminal and an input terminal respectively connected to the gate and a no ...


5
Shane C Hollmer, Chung You Hu, Binh Q Le, Pau ling Chen, Jonathan Su, Ravi Gutala, Colin Bill: Erase verify scheme for NAND flash. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin and Friel, December 28, 1999: US06009014 (137 worldwide citation)

The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates o ...


6
Eliot K Broadbent: Electroplating system with shields for varying thickness profile of deposited layer. Novellus Systems, Skjerven Morrill MacPherson Franklin and Friel, February 22, 2000: US06027631 (118 worldwide citation)

An electroplating system includes shield(s) to control the thickness profile of a metal electrodeposited onto a substrate. The shield(s) are positioned between the anode and the cathode in a standard electroplating apparatus with a device for rotating the plating surface. The cathode is rotated so t ...


7
David E Doggett: Laser diode/lens assembly. Bruce W McCaul, T Lester Wallace, Skjerven Morrill MacPherson Franklin and Friel, March 25, 1997: US05615052 (116 worldwide citation)

A laser diode/lens assembly wherein a lens (or multi-lens assembly) is immovably adhered to a housing of a laser diode package. The laser diode package may be a metal can style package having a substantially transparent window portion through which laser radiation is emitted when a laser diode insid ...


8
Wing Y Leung, Fu Chieh Hsu: Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system. Monolithic System Technology, Norman R Klivans, E Eric Hoffman, Skjerven Morrill MacPherson Franklin and Friel, January 7, 1997: US05592632 (112 worldwide citation)

A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together ...


9
Robert J Contolini, Jonathan Reid, Evan Patton, Jingbin Feng, Steve Taatjes, John Owen Dukovic: Electric potential shaping method for electroplating. Novellus Systems, International Business Machines, Skjerven Morrill MacPherson Franklin and Friel, December 12, 2000: US06159354 (109 worldwide citation)

An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thi ...


10
Alan P Aronoff, Marc S Birnkrant, Osamu Matsushima, Kyosuke Sugishita, Hisaharu Oba, Katta N Reddy, Richard I Olsen, Brent N Dichter: Testing and emulation of integrated circuits. NEC Electronics, Skjerven Morrill MacPherson Franklin and Friel, July 19, 1994: US05331571 (103 worldwide citation)

An architecture is provided for testing and emulating an integrated circuit with embedded function blocks. The output nodes of the function blocks are connected through a tri-state buffer to a test bus which in turn is connected to configurable external pins. The external pins multiplex the normal I ...