1
Mazur Martin, Hartig Carsten, Sulzer Georg: Method of defining the dimensions of circuit elements by using spacer deposition techniques. Advanced Micro Devices, sDRAKE Paul S, January 8, 2004: WO/2004/003977 (128 worldwide citation)

By using conventional spacer and etch techniques, microstructure elements, such as lines and contact openings of integrated circuits, may be formed with dimensions that are mainly determined by the layer thickness of the spacer layer. In a sacrificial layer (309), an opening is formed by means of st ...


2
Polzin R Stephen, Weber Frederick D, Talbot Gerald R, Hewitt Larry D, Reeves Richard W, Patel Shwetal A, La, Fetra Ross V, Gulick Dale E, Hummel Mark D, Miranda Paul C: A system including a host connected to a plurality of memory modules via a serial memory interconnect. Advanced Micro Devices, Polzin R Stephen, Weber Frederick D, Talbot Gerald R, Hewitt Larry D, Reeves Richard W, Patel Shwetal A, La, Fetra Ross V, Gulick Dale E, Hummel Mark D, Miranda Paul C, sDRAKE Paul S, November 25, 2004: WO/2004/102403 (17 worldwide citation)

A system (50) including a host (100) coupled to a serially connected chain of memory modules (150A-B). In one embodiment, each of the memory modules includes a memory control hub (160) for controlling access to a plurality of memory chips (261) on the memory module. The memory modules are coupled se ...


3
Horstmann Manfred, Pruefer Ekkehard, Buchholtz Wolfgang: A semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same. Advanced Micro Devices, Horstmann Manfred, Pruefer Ekkehard, Buchholtz Wolfgang, sDRAKE Paul S, May 11, 2006: WO/2006/049834 (8 worldwide citation)

By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in ...


4
Retersdorf Michael A: Product-related feedback for process control. Advanced Micro Devices, Retersdorf Michael A, sDRAKE Paul S, April 26, 2007: WO/2007/046945 (6 worldwide citation)

A method, apparatus, and a system for performing a product feedback for process control are provided. Metrology data relating to a first workpiece is received. An end of line parameter relating to the first workpiece is received. The end of line parameter is correlated with the metrology data. A pro ...


5
Sander Benjamin T, Ramani Krishnan V, Haddad Ramsey W, Alsup Mitchell: System and method for validating a memory file that links speculative results of load operations to register values. Advanced Micro Devices, Sander Benjamin T, Ramani Krishnan V, Haddad Ramsey W, Alsup Mitchell, sDRAKE Paul S, November 24, 2005: WO/2005/111794 (5 worldwide citation)

A system and method for linking speculative results of load operations to register values. A system (100) includes a memory file (132) including an entry (220) configured to store a first addressing pattern (206) and a first tag (208). The memory file (132) is configured to compare the first address ...


6
Hoentschel Jan, Wei Andy, Bloomquist Joe, Horstmann Manfred: An soi transistor having a reduced body potential and a method of forming the same. Advanced Micro Devices, Hoentschel Jan, Wei Andy, Bloomquist Joe, Horstmann Manfred, sDRAKE Paul S, November 8, 2007: WO/2007/126807 (4 worldwide citation)

By introducing an atomic species (11 IB), such as carbon, fluorine and the like, into the drain and source regions (115, 206), as well as in the body region (107, 207), the junction leakage of SOI transistors (110, 210M) may be significantly increased, thereby providing an enhanced leakage path (119 ...


7
Filippo Michael A, Pickett James K: Processor with dependence mechanism to predict whether a load is dependent on older store. Advanced Micro Devices, Filippo Michael A, Pickett James K, sDRAKE Paul S, March 16, 2006: WO/2006/028555 (4 worldwide citation)

A processor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler. The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C ...


8
Jaehne Rolf, Kluge Wolfram, Riedel Thorsten: Phase-locked loop with automatic frequency tuning. Advanced Micro Devices, sDRAKE Paul S, January 8, 2004: WO/2004/004126 (3 worldwide citation)

A PLL frequency synthesizer able to automatically set an appropriate operating mode of (Q) voltage controlled oscillator (4) is provided. The voltage controlled oscillator (4) is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled ...


9
Jones Gary K, Bode Christopher A, Edwards Richard D: Method and apparatus for overlay control using multiple targets. Advanced Micro Devices, sDRAKE Paul S, June 10, 2004: WO/2004/049072 (3 worldwide citation)

A method includes measuring a first overlay error between a first process layer (360) and a second process layer (340) using a first overlay target (330) formed on the second process layer (340). A second overlay error between the first process layer (360) and a third process layer (320) is measured ...


10
Wirbeleit Frank, Boschke Roman, Gerhardt Martin: Method for forming a strained transistor by stress memorization based on a stressed implantation mask. Advanced Micro Devices, Wirbeleit Frank, Boschke Roman, Gerhardt Martin, sDRAKE Paul S, February 7, 2008: WO/2008/016505 (3 worldwide citation)

By using an implantation mask having a high intrinsic stress, stress memorization technique (SMT) sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.



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