A method of monitoring an immersion lithography system (10) in which a wafer (12) can be immersed in a liquid immersion medium (24). The method detects an index of refraction of the immersion medium in a volume of the immersion medium through which an exposure pattern is configured to traverse and d ...
A method of operating an immersion lithography system (26), including steps of immersing at least a portion of a wafer (12) to be exposed in an immersion medium (24), wherein the immersion medium comprises at least one bubble (28); directing an ultrasonic wave (36) through at least a portion of the ...
A method of monitoring an immersion lithography system (10) in which a wafer (12) can be immersed in a liquid immersion medium (22) for exposure by an exposure pattern. The method detects the presence of a foreign body in the immersion medium to thereby determine if the immersion medium in a state t ...
A method for forming a semiconductor structure having a metal gate (30) with a controlled work function includes the step of forming a precursor having a substrate (10) with active regions (12) separated by a channel, a temporary gate (16) over the channel and within a dielectric layer (20). The tem ...
A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide (62, 64) that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the si ...
A semiconductor structure includes a fin (205) and a layer (305) formed on the fin. The fin (205) includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer (305) is formed on the surfaces and includes a second crystalline material. The first crystal ...
The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array (100, 200, 212, 300, 400). State change voltages can be applied to a single device in the array (100, 200, 212, 300, 400) of semiconductor devices wit ...
A narrow channel FinFET is described herein with a channel width of less than 6 nm. The FinFET may include a fin (140) in which the channel area is trimmed using a NH4OH etch or a reactive ion etch (RIE).
A hardmask stack is comprised of alternating layers of doped amorphous carbon (22) and undoped amorphous carbon (20). The undoped amorphous carbon layers (20) serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers (22) to prevent delamination ...
A memory cell (104) made of two electrodes(106, 202, 108, 204) with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media (110) contains an active low conductive layer (112) and passive layer (114). The controllably conductive media (110) changes ...
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