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Eugene Fitzgerald
Eugene A Fitzgerald: Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization. Massachusetts Institute of Technology, Samuels Gauthier & Stevens, August 22, 2000: US06107653 (138 worldwide citation)

A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer oil the at least one first layer. In another embodiment of the inv ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization. Massachusetts Institute of Technology, Samuels Gauthier & Stevens, September 18, 2001: US06291321 (121 worldwide citation)

A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the inve ...


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Eugene Fitzgerald
Eugene A Fitzgerald, Srikanth B Samavedam: Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon. Massachusetts Institute of Technology, Samuels Gauthier & Stevens, March 21, 2000: US06039803 (61 worldwide citation)

A method of processing semiconductor materials, including providing a monocrystalline silicon substrate having a (001) crystallographic surface orientation; off-cutting the substrate to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and epitaxially growing ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits. Samuels Gauthier & Stevens, September 12, 2002: US20020125497-A1 (4 worldwide citation)

Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits. Samuels Gauthier & Stevens, September 5, 2002: US20020123167-A1 (4 worldwide citation)

Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to ...


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Eugene Fitzgerald
Eugene A Fitzgerald: Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits. Samuels Gauthier & Stevens, September 5, 2002: US20020123183-A1 (3 worldwide citation)

Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to ...


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Eugene Fitzgerald
Eugene A Fitzgerald, Nicole Gerrish: CMOS inverter circuits utilizing strained silicon surface channel MOSFETS. Samuels Gauthier & Stevens, September 12, 2002: US20020125471-A1 (3 worldwide citation)

A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1xGex, layer on the Si substrate, and a strained surface layer on said relaxed Si1xGex, layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained su ...


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Eugene Fitzgerald
Eugene A Fitzgerald, Nicole Gerrish: CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs. Samuels Gauthier & Stevens, August 1, 2002: US20020100942-A1 (3 worldwide citation)

A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained su ...