1
Sik On Kong: Three dimensional IC package module. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, March 25, 2003: US06538333 (233 worldwide citation)

In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling ...


2
Igor V Peidous: Shallow trench isolation of MOSFETS with reduced corner parasitic currents. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, November 23, 1999: US05989978 (206 worldwide citation)

A method is described for forming MOSFETs with shallow trench isolation wherein the abrupt corners introduced by anisotropically etching the silicon trenches are modified by an oxidation step which rounds off the corners and also reduces the effect of tensile stresses caused by the densified trench ...


3
Seiki Ogura, Yutaka Hayashi: Nonvolatile memory cell, method of programming the same and nonvolatile memory array. Aalo LSI Design & Device Technology, George O Saile, Stephen B Ackerman, Rosemary L S Pike, July 3, 2001: US06255166 (186 worldwide citation)

Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to ...


4
Cher Liang Cha, Alex See, Lap Chan: Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, October 16, 2001: US06303418 (162 worldwide citation)

A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator ...


5
Shyue Fong Quek, Ying Keung Leung, Sang Yee Loong, Ting Cheong Ang: Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, December 10, 2002: US06492726 (153 worldwide citation)

In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package a ...


6
Vladislav Vassiliev: Method of silicon oxide and silicon glass films deposition. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, William J Stoffel, March 6, 2001: US06197705 (127 worldwide citation)

A method for fabricating a silicon oxide and silicon glass layers at low temperature using soft power-optimized Plasma-Activated CVD with a TEOS-ozone-oxygen reaction gas mixture (TEOS O


7
Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek: Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, Stephen G Stanton, October 9, 2001: US06300177 (124 worldwide citation)

A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a por ...


8
Seiki Ogura, Yutaba Hayashi, Tomoko Ogura: Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory. Halo LSI Design & Device Technology, George O Saile, Stephen B Ackerman, Rosemary L S Pike, June 19, 2001: US06248633 (120 worldwide citation)

A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short co ...


9
Jin Yuan Lee, Mou Shiung Lin: Method for making high-performance RF integrated circuits. Megic Corporation, George O Saile, Stephen B Ackerman, Rosemary L S Pike, July 6, 2004: US06759275 (119 worldwide citation)

A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created ...


10
Lap Chan, Hou Tee Ng: Method for planarized interconnect vias using electroless plating and CMP. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, October 24, 2000: US06136693 (118 worldwide citation)

An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating ...



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