1
Jeffrey F Hughes, John S Liptay, James W Rymarczyk, Stanley E Stone: Multi-instruction stream branch processing mechanism. International Business Machines Corporation, Robert W Berray, April 29, 1980: US04200927 (206 worldwide citation)

In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from ...


2
Andrew R Heller, William S Worley Jr: Authorization mechanism for transfer of program control or data between different address spaces having different storage protect keys. International Business Machines, Robert W Berray, December 28, 1982: US04366537 (129 worldwide citation)

Permits one program in one address space to obtain access to data in another address space or to call a program in another address space without invoking a supervisor, with authorization to use a storage protect key other than that specifically assigned to the program by a supervisor when in a new s ...


3
William H Greer: Vehicle identification and position signalling system in a public transportation system. Robert W Berray, September 21, 1982: US04350969 (72 worldwide citation)

Each vehicle of a transportation system is provided with a radio transmitter providing electable and different sequences of signals, one part of the signal identifying the vehicle, and another changing sequence of signals, either under operator control or automatically by attachment to the odometer, ...


4
Daniel B Martin: Instruction substitution mechanism in an instruction handling unit of a data processing system. International Business Machines, Robert W Berray, March 27, 1984: US04439828 (65 worldwide citation)

Buffered, pre-fetched instructions in the instruction handling portion of a data processing system are examined to detect sequences of predetermined instructions to effect generation of a substitute instruction to be executed by an execution unit in place of the first instruction of the sequence to ...


5
James A Cannavino, Andrew R Heller, Morris Taradalsky, William S Worley Jr: Authorization mechanism for establishing addressability to information in another address space. International Business Machines, Robert W Berray, February 7, 1984: US04430705 (55 worldwide citation)

Permits one program in one address space to obtain access to data in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. Addressability to a second address space may be ...


6
Max Abbott Bouknecht, Michael Ian Davis, Louis Peter Vergari: Input/output interface logic for concurrent operations. International Business Machines Corporation, Robert W Berray, July 26, 1977: US04038642 (53 worldwide citation)

The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data, and includes logic in a peripheral device control unit for dynamic change of the attached peripheral device interrupt priority level while the device may be ...


7
Rudolph N Rechtschaffen: Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction. International Business Machines, Robert W Berray, March 4, 1986: US04574349 (48 worldwide citation)

Each of a plurality of stored pointers identifies and accesses one of a plurality of hardware registers in a central processing unit (CPU). Each pointer is associated with and corresponds to one of a limited number of general purpose registers addressable by various fields in a program instruction o ...


8
Hirotoshi Jitsukawa, Tsutomu Maruyama: Method of error detection and correction by majority. International Business Machines, Robert W Berray, June 2, 1987: US04670880 (38 worldwide citation)

According to the present invention, each data (one byte data in the embodiments described below) is transferred three times in total. The original data is transferred as it is on one time, a data made by inverting the original data is transferred on another time, and a data made by permuting all bit ...


9
Guy G Duforestel, Michel A Lechaczynski, Clement Y Poiraud, Paul P Viallon: Device for serializing/deserializing bit configurations of variable length. International Business Machines Corporation, Robert W Berray, July 14, 1987: US04680733 (37 worldwide citation)

A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n.


10
David A Elko, Jeffrey A Frey, Audrey A Helffrich, Jeffrey M Nick, Michael D Swanson: Command quiesce function. International Business Machines Corporation, Floyd A Gonzalez, Robert W Berray, August 16, 1994: US05339405 (36 worldwide citation)

One or more Central Processing Complexes (CPC), each with one or more programs being executed, become command initiators by issuing commands requesting an action to be performed by a command responder. The responder is a Structured Electronic Storage (SES) which comprises a coupling facility. The SE ...



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