William B Ledbetter Jr, Russell A Reininger: Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation. Motorola, Robert L King, June 2, 1992: US05119485 (166 worldwide citation)

A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory r ...



James Wesley Miller, Cynthia Ann Torres, Troy L Cooper: Circuit for electrostatic discharge protection. Motorola, Robert L King, August 31, 1999: US05946177 (116 worldwide citation)

A circuit (100) ensures electrostatic discharge (ESD) protection during an ESD event. The ESD circuit (100) has a current shunting device (135), a RC trigger circuit (125) and a RC delay circuit (130). The shunting device (135) is connected between two IC power supply rails, and provides the primary ...

James K Schaeffer, Darrell Roan, Dina H Triyoso, Olubunmi O Adetutu: Method for treating a semiconductor surface to form a metal-containing layer. Freescale Semiconductor, Joanna G Chiu, Robert L King, November 7, 2006: US07132360 (111 worldwide citation)

A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely ...

Rana P Singh, Paul A Ingersoll: Semiconductor device structure and method for forming. Motorola, James L Clingan Jr, Robert L King, February 11, 2003: US06518146 (105 worldwide citation)

A semiconductor device has both a logic section and a non-volatile memory (NVM) section. Transistors in both sections are separated by trench isolation. The logic isolation has narrower trenches than NVM trenches and both types of trenches have corners at the tops thereof. The trenches are lined by ...


James M Sibigtroth, George L Espinor, Bruce L Morton: Memory bit line segment isolation. Freescale Semiconductor, Robert L King, David G Dolezal, May 9, 2006: US07042765 (94 worldwide citation)

A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being era ...

Kevin L Kloker, Ronald H Cieslak: X.times.Y Bit array multiplier/accumulator circuit. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, Robert L King, March 11, 1986: US04575812 (94 worldwide citation)

An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and sy ...

Shawn M O&apos Connor, Mark Allen Gerber, Jean Desiree Miller: Packaged semiconductor with multiple rows of bond pads and method therefor. Motorola, James L Clingan Jr, Robert L King, November 5, 2002: US06476506 (92 worldwide citation)

A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond pads on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively low ...