1
Melanie M Chow, John E Cronin, William L Guthrie, Carter W Kaanta, Barbara Luther, William J Patrick, Kathleen A Perry, Charles L Standley: Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias. International Business Machines Corporation, Robert J Haase, John A Stemwedel, December 6, 1988: US04789648 (313 worldwide citation)

Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive mat ...


2
Klaus D Beyer, James S Makris, Eric Mendel, Karen A Nummy, Seiki Ogura, Jacob Riseman, Nivo Rovedo: Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique. International Business Machines Corporation, Robert J Haase, June 9, 1987: US04671851 (145 worldwide citation)

A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based s ...


3
William Arthur Warwick: Semiconductor integrated circuit devices. International Business Machines Corporation, Robert J Haase, May 3, 1977: US04021838 (108 worldwide citation)

A power bus element for use in large scale integrated circuits is described. Each bus element consists, for example, of a chip of silicon having two levels of metallization thereon, one acting as an earth (or ground) return plane and the other providing power voltages. Dependent contacts on the chip ...


4
Philip M Ryan: System for updating error map of fault tolerant memory. International Business Machines Corporation, Richard E Cummins, Robert J Haase, October 23, 1984: US04479214 (105 worldwide citation)

An online system is disclosed for mapping errors into an error map as data is transferred between a CPU and a relatively large fault tolerant semiconductor memory system without interfering with the normal use of the memory. The error mapping system permits a fault alignment exclusion mechanism to d ...


5
Roger L Verkuil: Contactless electrical thin oxide measurements. International Business Machines Corporation, Robert J Haase, Charles W Peterson Jr, January 16, 1996: US05485091 (101 worldwide citation)

A method for measuring the thickness of very thin oxide layers on a silicon substrate. A corona discharge source repetitively deposits a calibrated fixed charge density on the surface of the oxide. The resultant change in oxide surface potential for each charge deposition is measured. By choosing a ...


6
James A Bondur, Hans B Pogge: Reactive ion etching method for producing deep dielectric isolation in silicon. International Business Machines Corporation, Robert J Haase, February 13, 1979: US04139442 (100 worldwide citation)

A method for producing deeply recessed oxidized regions in silicon. A series of deep trenches are formed in a silicon wafer by a reactive ion etching (RIE) method. In a first species, the trenches are of equal width. A block-off mask is selectively employed during part of the RIE process to produce ...


7
Charles J Kraus, Herbert I Stoller, Leon L Wu: Multilayered interposer board for powering high current chip modules. International Business Machines Corporation, Robert J Haase, August 18, 1987: US04688151 (76 worldwide citation)

A multilayered interposer powering board is disclosed for the distribution of required voltage levels to integrated circuit chip modules under conditions of high current demand and heat induced expansions. The interposer board is introduced between the module and its module mounting board. Flexible ...


8
Cheng T Horng, Robert O Schwenker: Process for making large area isolation trenches utilizing a two-step selective etching technique. International Business Machines Corporation, Robert J Haase, July 8, 1980: US04211582 (73 worldwide citation)

A method for making wide, deep recessed oxide isolation trenches in silicon semiconductor substrates. A semi-conductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizo ...


9
Jack R Franco, Janos Havas, Lewis J Rompala: Method for forming patterned films utilizing a transparent lift-off mask. International Business Machines Corporation, Robert J Haase, January 18, 1977: US04004044 (68 worldwide citation)

A lift-off method for use in depositing thin films in the fabrication of integrated circuits which avoids edge tearing of the films. The method involves depositing an organic polymeric first masking material on a substrate, and forming on said material a layer of a polydimethylsiloxane resin materia ...


10
George R Goth, Thomas A Hansen, James S Makris: Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices. International Business Machines Corporation, Robert J Haase, October 29, 1985: US04549927 (53 worldwide citation)

Deep trenches (14,15) are formed according to the desired pattern through the N epitaxial layer (13) and N.sup.+ subcollector region (12) into the P.sup.- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon ma ...